• Journal of Korea Multimedia Society
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• v.2 no.4
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• pp.367-377
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• 1999

Nowadays, the number of database applications which need fast transaction processing are increasing. One way to improve the performance of transaction processing is to reside the whole database in main memory As semiconductor memory becomes cheaper and chip densities increase, the research to improve transaction throughput rates of transaction processing system, using main memory databases, has begun In this thesis, how to implement a high performance transaction processing system based on main memory databases, new concurrency control scheme, recovery scheme and storage structure is presented. The objective of the proposed schemes is to improve the transaction processing system performance measured by transaction throughput and response times.

• Journal of Biosystems Engineering
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• v.26 no.2
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• pp.177-188
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• 2001

This research was carried out to examine the optimum design conditions of a vertical small-scale milling machine where the rough rice is processed directly into the white rice in one pass. Effects of the main spindle speed, feed screw pitch and ceramic coating length of the roller on various milling characteristics such as white rice processing capacity, electric energy consumption, rice temperature increase, broken rice ratio, moisture reduction, outlet force and crack ratio increase were studied. The results are as follows. 1. The maximum white rice processing capacity and the lowest crack ratio increase, were obtained from a machine with specification: main spindle speed of 970rpm having a feed screw pitch of 19㎜. 2. The minimum electric energy consumption was obtained with the main spindle speeds of 900 and 970rpm respectively having a feed screw pitch of 19㎜. 3. The rice temperature was increased as the feed screw pitch decreased and the main spindle speed increased. 4. Broken rice ratio was relatively low with the range of 0.8∼1.3%. 5. Moisture content loss was with the range of 0.05∼0.4%. 6. The highest outlet force was 0.72kg$\_$f/ with 900rpm of the main spindle speed and 19㎜ of the feed screw pitch and the lowest outlet force was 0.18∼0.34kg$\_$f/ with 970rpm of the main spindle speed and 16㎜ of the feed screw pitch. 7. The optimum design conditions for the vertical small-scale milling machine were obtained at 970rpm of the main spindle speed, 19㎜ of the feed screw pitch and 20㎜ of the ceramics coating length.

• Journal of Institute of Control, Robotics and Systems
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• v.3 no.6
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• pp.626-631
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• 1997

This paper represents the design of a real-time image preprocessing system. The preprocessing system performs hardware-wise mask operations and thresholding operations at the speed of camera output single rate. The preprocessing system consists of the preprocessing board and the main processing board. The preprocessing board includes preprocessing unit that includes a $5\times5$ mask processor and LUT, and can perform mask and threshold operations in real-time. To achieve high-resolution image input data($20485\timesn$), the preprocessing board has a linescan camera interface. The main processing board includes the image processor unit and main processor unit. The image processor unit is equipped with TI's TMS320C32 DSP and can perform image processing algorithms at high speed. The main processor unit controls the operation of total system. The proposed system is faster than the conventional CPU based system.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.544-547
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• 2007

Because data processing systems in recent years are more complicated, main function of the data processing is divided as several sub-functions which are implemented and verified in each subsystem of the data processing system. For the verification of data processing system, many interface tests among subsystems are required and also a lot of simulation systems are demanded. This paper proposes CTHS (Common Test Harness System) for satellite ground segment development which has all of functions for interface test of the data processing system in one PC. Main functions of the CTHS software are data interface, system log generation, and system information display. For the interface test of the data processing system, all of actions of the CTHS are executed by a pre-defined operation scenario which is written by purpose of the data processing system test.

• Cartoon and Animation Studies
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• s.40
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• pp.243-260
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• 2015

Being a symbolic image to let traditional 'mother wonlee' contents characters known widely, need to be made in a way that can deliver the powerful message of korea An-dong traditional local contents and the value of regent story. As for the contents character develope methods and the scope of the study, an theoretical study was conducted based on literature review, and, factor plus fiction field surveys, and the legend story and then an effect of character marketing on global contents with original identity. 'mother wonlee' pre-production plaining have been analysis with creative described based on the ancients features and the classification of ancient original characters, and the situation and the concept of An-dong local place. as a results this thesis is show up how to make up a main character develop processing and make a features design processing of the characters who different age and a scenes. as a conclusion is drawing about a 'Wonlee' and 'Eungtea' both main Character plaining processing and graphics; traditional face, all clothes, body proportion, etc. Also we trade to traditional patten with character planing. it will be a high value industry which facilitates a variety of industries in conjunction with marketing traditional source characters in global. Recognizing the value of traditional story main character design and graphics marketing and utilizing the value through various media will create infinite value, enabling the global marketing.

• Proceedings of the Korean Society of Medical Physics Conference
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• 2002.09a
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• pp.121-122
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• 2002

The main principle of radiation therapy is to deliver optimum dose to tumor to increase tumor cure probability while minimizing dose to critical normal structure to reduce complications. RTP system is required for proper dose plan in radiation therapy treatment. The main goal of this research is to develop dose model for photon, electron, and brachytherapy, and to display dose distribution on patient images with optimum process. The main items developed in this research includes: (l) user requirements and quality control; analysis of user requirement in RTP, networking between RTP and relevant equipment, quality control using phantom for clinical application (2) dose model in RTP; photon, electron, brachytherapy, modifying dose model (3) image processing and 3D visualization; 2D image processing, auto contouring, image reconstruction, 3D visualization (4) object modeling and graphic user interface; development of total software structure, step-by-step planning procedure, window design and user-interface. Our final product show strong capability for routine and advance RTP planning.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• The Transactions of the Korea Information Processing Society
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• v.7 no.6
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• pp.1753-1765
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• 2000

As the areas of computer application are expanded, real-time application environments that must process as many transactions as possible within their deadlines, such as a stock transaction systems, ATM switching systems etc, have been increased recently. The reason why the conventional database systems can't process soft real-time applications is the lack of prediction and poor performance on processing transaction's deadline. If transactions want to access data stored at the secondary storage, they can not satisfy requirements of real-time applications because of the disk delay time. This paper designs a main-memory database prototype systems to be suitable to real-time applications and then this system can produce rapid results without disk i/o as all of the information are loaded in main memory database. In thesis proposed the improved techniques with respect to logging, checkpointing, and recovering in our environment. In order to improve the performance of the system, a) the frequency of log analysis and redo processing is reduced by the proposed redo technique at system failure, b) database consistency is maintained by improved fuzzy checkpointing. The performance model is proposed which consists of two parts. The first part evaluates log processing time for recovery and compares with other research activities. The second part examines checkpointing behavior.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11A
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• pp.1963-1970
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• 2001

It is essential design process to analyze processing method and set out top level HW configuration using main parameters before implementation of the SAR processor. This paper identifies the impact of the I/O and algorithm structure upon the parallel processing to be assessed and suggests the practical mapping method fur parallel processing to the SAR data. Also, simulation is performed to the E-SAR processor to examine the usefulness of the method, and the results are analyzed and discussed.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.2
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• pp.178-184
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• 2004

In this paper, we designed an image processing system for the high speed line-scan camera which adopts the new memory model we proposed. As a resolution and a data rate of the line-scan camera are becoming higher, the faster image processing systems are needed. But many conventional systems are not sufficient to process the image data from the line-scan camera during a very short time. We designed the memory controller which eliminates the time for transferring image data from the line-scan camera to the main memory with high-speed SRAM and has a dual-port configuration therefore the DSP can access the main memory even though the memory controller are writing the image data. The memory controller is implemented by VHDL and Xilinx SPARTAN-IIE FPGA.