• Proceedings of the Korea Information Processing Society Conference
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• 2003.05b
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• pp.1117-1120
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• 2003

DWDM(DensedWavelengthDivisionMultiplexing)은 광 파이버를 이용하여 기존의 통신보다 높은 대역폭(B/W)을 얻기 위한 기술로 여러 신호를 각각 다른 파장으로 변조해 하나의 Fiber 를 통해 전송하는 방식이며, 기본적으로 EDFA(Erbium Doped Fiber Amplifier), AWG(Arrayed Wave guide Grating), OADM(Optical Add/Drop Multiplexer) 등의 주요 부품과 여러 광 관련 부품들로 구성돼 있으며, 다수의 파장을 MUX(AWG)에서 다중화하고, 장거리 전송을 위해 OA(EDFA)에서 광신호를 증폭하게 된다 그리고 일부 특정 파장만 Add/Drop하기 위해 OADM이 놓이게 되며, 또한 선로(광섬유)의 손실을 보상하기 위해 필요한 구간에 리피터(EDFA)를 두어 광신호를 증폭 송신하며 수신단에서는 들어오는 여러 파장을 OA(EDFA)를 통해 증폭한 후 DEMUX(AWG)에서 역 다중화해 수신하게 된다. 이와 같은 DWDM방식을 이용한 Network는 Star, Mesh, Ring 등의 다양한 형태로 구성될 수 있으며, 초기에는 Point-to-Point 방식의 장거리 전송에 주로 사용돼 왔으나 Metro 구간의 Traffic 이 급격히 증가하면서 Metro- DWDM Network 이 부각되고 있어 본 논문에서는 현재 SK Telecom에서 상용화되고 있는 1,600G DWDM과 Metro-DWDM간의 망 구축의 최적화 방안을 연구해 본다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.4
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• pp.35-41
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• 2000

In this paper, the multiplicative algorithm of two polynomals over finite field GF(2$^{m}$ ) is presented. The proposed algorithm permits an efficient realization of the parallel multiplication using iterative arrays. At the same time, it permits high-speed operation. This multiplier is consisted of three operation unit: multiplicative operation unit, the modular operation unit, the primitive irreducible operation unit. The multiplicative operation unit is composed of AND gate, X-OR gate and multiplexer. The modular operation unit is constructed by AND gate, X-OR gate. Also, an efficient pipeline form of the proposed multiplication scheme is introduced. All multipliers obtained have low circuit complexity permitting high-speed operation and interconnection of the cells are regular, well-suited for VLSI realization.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1288-1293
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• 2005

This paper presents a design method for multiple-output combinational digital logic systems using time domain based on multiplexing(TDBM) and common multi-terminal extension decision diagrams(CMTEDD). The CMIEDDs represents extension valued multiple-output functions, while TDBM systems transmit several signals on a single lines. The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams(CBDDs) and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams(CMTBDD) from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.2
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• pp.213-221
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• 2011

Avionics system tends to be designed to have the integrated architecture, and it is getting difficult and complex to verify the flight-critical function because of sophisticated structure. In Korean Utility Helicopter, mission computer acts as the MUX Bus Controller to handle the data from both communication, identification, mission/display and survivability equipment inside Mission Equipment Package and aircraft subsystems such as fuel system and electrical system while it is interfacing with Automatic Flight Control System and Full-Authority Digital Engine Control via ARINC-429 bus. The Flight Displays which is classified as flight-critical function in aircraft is implemented on Primary Flight Display after mission computer processes data from AFCS in order to generate graphics. This paper defines the flight-critical function implemented in mission computer for KUH, and presents the static and dynamic test procedures which is performed on System Integration Laboratory along with Playback Recorder prior to flight test.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.263-266
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• 2012

This paper describes an efficient hardware implementation of Whirlpool hash function as ISO/IEC 10118-3 standard. Optimized timing is achieved by using pipelined small LUTs, and Whirlpool block cipher and key schedule have been implemented in parallel for improving throughput. In key schedule, key addition is area-optimized by using inverters and muxes instead of using rom and xor gates. This hardware has been implemented on Virtex5-XC5VSX50T FPGA device. Its maximum operating frequency is about 151MHz, and throughput is about 950Mbps.

• Journal of Information Display
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• v.11 no.2
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• pp.76-83
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• 2010

This paper presents the multi-user autostereoscopic 3D display system constructed and operated by the authors using the time-multiplexing approach. This prototype has three main advantages over the previous versions developed by the authors: its hardware was simplified as only one optical array is used to create viewing regions in space, a lenticular multiplexing screen is not necessary as images can be produced sequentially on a fast 120Hz LCD with full resolution, and the holographic projector was replaced with a high-frame-rate digital micromirror device (DMD) projector. The whole system in this prototype consists of four major parts: a 120Hz high-frame-rate DMD projector, a 49-element optical array, a 120Hz screen assembly, and a multi-user head tracker. The display images for the left/right eyes are produced alternatively on a 120Hz direct-view LCD and are synchronized with the output of the projector, which acts as a backlight of the LCD. The novel steering optics controlled by the multiuser head tracker system directs the projector output to regions referred to as exit pupils, which are located in the viewers’eyes. The display can be developed in the "hang-on-the-wall"form.

• Journal of Communications and Networks
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• v.4 no.2
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• pp.128-135
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• 2002

We propose a new space priority mechanism, and analyze its performance in a single Constant Bit Rate (CBR) server. The arrival process is derived from the superposition of two types of traffics, each in turn results from the superposition of homogeneous ON-OFF sources that can be approximated by means of a two-state Markov Modulated Poisson Process (MMPP). The buffer mechanism enables the Asynchronous Transfer Mode (ATM) layer to adapt the quality of the cell transfer to the Quality of Service (QoS) requirements and to improve the utilization of network resources. This is achieved by "Selective-Delaying and Pushing-ln"(SDPI) cells according to the class they belong to. The scheme is applicable to schedule delay-tolerant non-real time traffic and delay-sensitive real time traffic. Analytical expressions for various performance parameters and numerical results are obtained. Simulation results in term of cell loss probability conform with our numerical analysis.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.2
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• pp.124-130
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• 2005

In this paper, low-power design and implementation techniques for DWT(Discrete Wavelet Transform) of the JPEG2000 compression are proposed. In DWT block of the JPEG2000, linear phase 9 tap and 7 tap filters are used. For low-power implementation of those filters, processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized. Proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of the binary values of filter coefficient. Finally, in third block, multiplied values are output and stored in flip-flop train. For comparison of the implementation area and power dissipation, proposed and conventional structures are implemented by using Verilog-HDL coding. In simulation, it is shown that 53.1% of the implementation area can be reduced comparison with those of the conventional structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.4
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• pp.273-279
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• 2000

Electrical repair method which has replaced laser repair method can replace defective cell by redundancy’s in the redundancy scheme of conventional high density memory. This electrical repair circuit consists of the antifuse program/read/latch circuits, a clock generator a negative voltage generator a power-up pulse circuit a special address mux and etc. The measured program voltage of made antifuses was 7.2~7.5V and the resistance of programmed antifuses was below 500 Ω. The period of clock generator was about 30 ns. The output voltage of a negative voltage generator was about 4.3 V and the current capacity was maximum 825 $mutextrm{A}$. An antifuse was programmed using by the electric potential difference between supply-voltage (3.3 V) and output voltage generator. The output pulse width of a power-up pulse circuit was 30 ns ~ 1$mutextrm{s}$ with the variation of power-up time. The programmed antifuse resistance required below 44 ㏀ from the simulation of antifuse program/read/latch circuit. Therefore the electrical repair circuit behaved safely and the yield of high densitymemory will be increased by using the circuit.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.12
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• pp.64-70
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• 2008

In case that conventional PRC(Pseudo-Randomized Frequency Carrier) modulation scheme is applied to a three-phase HBML(H-Bridge Multi-Level Inverter), the dominant harmonics spectra appear at twice switching frequency. In this paper, the dominant harmonics spectra spreading effect of the conventional PRC scheme was improved by using three stage MUXs(Multiplexers) and two triangular carriers with fixed frequency which has mutual relation of the twice frequency. To confirm the validity of the improved PRC scheme, the experiment were performed on a 1.5[kw] three-phase HBML based induction motor drives. And, the harmonics spectra of the conventional and improved PRC schemes are compared and discussed.