• Title/Summary/Keyword: MPW

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MPW Implementation of Crypto-processor Supporting Block Cipher Algorithms of PRESENT/ARIA/AES (블록 암호 알고리즘 PRESENT/ARIA/AES를 지원하는 암호 프로세서의 MPW 구현)

  • Cho, Wook-lae;Kim, Ki-bbeum;Bae, Gi-chur;Shin, Kyung-wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.10a
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    • pp.164-166
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    • 2016
  • PRESENT/ARIA/AES의 3가지 블록 암호 알고리즘을 지원하는 암호 프로세서를 MPW(Multi-Project Wafer)칩으로 구현하였다. 설계된 블록 암호 칩은 PRmo(PRESENT with mode of operation) 코어, AR_AS(ARIA_AES) 코어, AES-16b 코어로 구성된다. PRmo는 80/128-비트 마스터키와, ECB, CBC, OFB, CTR의 4가지 운영모드를 지원한다. 128/256-비트 마스터키를 사용하는 AR_AS 코어는 서로 내부 구조가 유사한 ARIA와 AES를 통합하여 설계하였다. AES-16b는 128-비트 마스터키를 지원하고, 16-비트 datapath를 채택하여 저면적으로 구현하였다. 설계된 암호 프로세서를 FPGA검증을 통하여 정상 동작함을 확인하였고, 0.18um 표준 셀 라이브러리로 논리 합성한 결과, 100 KHz에서 52,000 GE로 구현이 되었으며, 최대 92 MHz에서 동작이 가능하다. 합성된 다중 암호 프로세서는 MPW 칩으로 제작될 예정이다.

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MPW Chip Implementation and Verification of High-performance Vector Inner Product Calculation Circuit for SVM-based Object Recognition (SVM 기반 사물 인식을 위한 고성능 벡터 내적 연산 회로의 MPW 칩 구현 및 검증)

  • Shin, Jaeho;Kim, Soojin;Cho, Kyeongsoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.11
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    • pp.124-129
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    • 2013
  • This paper proposes a high-performance vector inner product calculation circuit for real-time object recognition based on SVM algorithm. SVM algorithm shows a higher detection rate than other object recognition algorithms. However, it requires a huge amount of computational efforts. Since vector inner product calculation is one of the major operations of SVM algorithm, it is important to implement a high-performance vector inner product calculation circuit for real-time object recognition capability. The proposed circuit adopts the pipeline architecture with six stages to increase the operating speed and makes it possible to recognize objects in real time based on SVM. The proposed circuit was described in Verilog HDL at RTL. For silicon verification, an MPW chip was fabricated using TSMC 180nm standard cell library. The operation of the implemented MPW chip was verified on the test board with test application software developed for the chip verification.

Design and MPW Implementation of 3D Graphics Floating Point Ips (3차원 그래픽용 부동 소수점 연산기 IP 설계 및 MPW 구현)

  • Lee, Jung-Woo;Kim, Ki-Chul
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.987-988
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    • 2006
  • This paper presents a design and MPW implementation of 3D Graphics Floating Point IPs. Designed IPs include adder, subtractor, multiplier, divider, and reciprocal unit. The IPs have pipelined structures. The IPs meet the accuracy required in OpenGL ES. The operation frequency of the IPs is 100MHz. The IPs can be efficiently used in 3D graphics accelerators.

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A Development of Experimental Model Prediction of Leakage Pressure in MPW (전자기 펄스 용접시 누수압력을 예측하기 위한 실험모델의 개발)

  • Shim, Ji-Yeon;Kim, Ill-Soo;Kim, In-Ju;Kang, Bong-Yong
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.18 no.6
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    • pp.652-657
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    • 2009
  • MPW(Magnetic Pulse Welding) is a technologies for welding of metals by means of repulsive force on account of the interaction between electro-magnetic field of coil and current induced in outer pipe. These MPW is one of the most useful welding process of welding ability of the dissimilar metal in which cylindrical materials, such as pipe, tube. As the quality of a weld joint is strongly influenced by process parameters during the welding process and the success of the welding to evaluated according to the leakage pressure. Generally, the process parameters is magnetic pressure, the gap between outer pipe and inner pipe, and the ratio of thickness to diameter of pipe(D/T) in MPW. Therefore, the goal of this study was to explain the effect of parameters on the weld joint leakage pressure. For these purposes, FFD(Fractional Factorial Design) were used for the experiment. The measured data were analyzed by regression analysis and verification experiments with random condition were conducted to confirm the suggested experimental model.

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Review of magnetic pulse welding

  • Kang, Bong-Yong
    • Journal of Welding and Joining
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    • v.33 no.1
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    • pp.7-13
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    • 2015
  • Magnetic pulse welding(MPW) is a solid state welding process that is accomplished by a magnetic pulse causing a high-velocity impact on two materials, resulting in a true metallurgical bond. One of the great advantages of MPW is that it is suitable for joining dissimilar metals. No heat affected zones are created because of the negligible heating and the clean surfaces formation that is a consequence of the jet and the metal is not degraded. Also, compared to other general welding processes, this process leads to only a low formation of brittle intermetallic compounds However, although this process has many advantages its application to industrial fields has so far been very low. Therefore, in this study we are presenting the principles, apparatus and application of MPW for application the industrial fields.

Effects of the Stand-off Distance on the Weld Strength in Magnetic Pulse Welding (전자기펄스용접에서 용접강도에 미치는 접합간격의 영향)

  • Kim, Sung-Wook;Chun, Chang-Keun;Kim, Sook-Hwan
    • Journal of Welding and Joining
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    • v.26 no.6
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    • pp.48-53
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    • 2008
  • Although Magnetic Pulse Welding(MPW) is not a recently developed technique, it has gained the attention of the automotive industry. MPW has become an accepted welding process because it enables the joining of similar, and dissimilar materials, with a very short cycle time, without the need for filler metal and gases. In this study, the effect of the stand-off distance on the weld strength has been investigated. The compressive strength of the MPW joints was evaluated using UTM. The interface of weld, IMC composition and morpology were studied by SEM and EDS. It was concluded that the stand-off distance and the voltage are the main parameters influencing the strength of weld. In case of too high stand-off distance, it influenced harmful effect because of the resistance of deformation.

Implementation of Encryption Module for Securing Contents in System-On-Chip (콘텐츠 보호를 위한 시스템온칩 상에서 암호 모듈의 구현)

  • Park, Jin;Kim, Young-Geun;Kim, Young-Chul;Park, Ju-Hyun
    • The Journal of the Korea Contents Association
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    • v.6 no.11
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    • pp.225-234
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    • 2006
  • In this paper, we design a combined security processor, ECC, MD-5, and AES, as a SIP for cryptography of securing contents. Each SIP is modeled and designed in VHDL and implemented as a reusable macro through logic synthesis, simulation and FPGA verification. To communicate with an ARM9 core, we design a BFM(Bus Functional Model) according to AMBA AHB specification. The combined security SIP for a platform-based SoC is implemented by integrating ECC, AES and MD-5 using the design kit including the ARM9 RISC core, one million-gate FPGA. Finally, it is fabricated into a MPW chip using Magna chip $0.25{\mu}m(4.7mm{\times}4.7mm$) CMOS technology.

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DFT Conformational Study of Calix[6]arene: Hydrogen Bond

  • Kim, Kwang-Ho;Choe, Jong-In
    • Bulletin of the Korean Chemical Society
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    • v.30 no.4
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    • pp.837-845
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    • 2009
  • We have performed DFT calculations to investigate the conformational characteristics and hydrogen bonds of the calix[6]arene (1) and p-tert-butylcalix[6]arene (2). The structures of various conformers of 1 were optimized by using the B3LYP/6-31G(d,p) and /6-31+G(d,p) methods followed by single point calculation of MPW1PW91/ 6-31G(d,p). The relative stability of the conformers of 1 is in the following order: cone (pinched: most stable) > partial-cone > cone (winged) $\sim$ 1,2-alternate $\sim$ 1,2,3-alternate > 1,4-alternate > 1,3-alternate > 1,3,5-alternate. The structures of different conformers of 2 were optimized by using the B3LYP/6-31G(d,p) method followed by single point calculation of MPW1PW91/6-31G(d,p). The relative stability of the conformers of 2 is in the following order: cone (pinched) > 1,2-alternate > cone (winged) > 1,4-alternate $\sim$ partial-cone > 1,2,3-alternate > 1,3,5alternate > 1,3-alternate. One of the important factors affecting the relative stabilities of the various conformers of the 1 and 2 is the number and strength of the intramolecular hydrogen bonds.

Selection of Optimal Process Parameters for Al/Steel Joining Using a MPW (전자기 펄스 용접을 이용한 Al/Steel 접합시 최적의 공정변수 선정)

  • Shim, Ji-Yeon;Kang, Bong-Yong;Kim, Ill-Soo;Lee, Kwang-Jin;Kim, In-Ju
    • Proceedings of the KWS Conference
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    • 2010.05a
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    • pp.47-47
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    • 2010
  • 지구온난화의 심화로 사회적으로 환경의 중요성에 대한 인식이 확산되면서 $CO_2$ 배기가스 및 연비와 직결되어 있는 자동차 중량 절감의 중요성이 강조됨에 따라 차체 경량화 기술은 환경 친화적인 자동차 개발의 핵심기술로 연구되고 있다. 그러나 충돌보호 장치 및 편의장치의 증가로 차체 중량은 지속적으로 증가하고 있어 차체 중량을 혁신적으로 절감할 수 있는 초경량 차체기술이 요구된다. 차체 경량화 방법으로 기존 강재를 알루미늄재로 대체하는 방안이 연구되고 있으며, 일부 해외 고급 차종에서 알루미늄재를 이용한 스페이스 프레임 및 부품 개발을 검토 적용 중이다. 그러나 알루미늄 단일재 사용은 안전성등에서 요구 성능을 만족시키기 어렵기 때문에 강재와 알루미늄재의 적절한 사용이 필요하다. 이를 위하여 강재와 알루미늄간 이종접합부가 발생하며 이를 위한 적정 공정 개발이 필요하다. 전자기 펄스 용접(MPW)은 고상접합의 한 종류로서 고전류를 순간적으로 방전하여 발생된 고에너지를 통하여 접합이 이루어진다. 이러한 고에너지는 외부재의 전 자기적 성질에 의하여 에너지량이 결정되므로 외부재의 전도도(conductivity)는 매우 중요하며 이러한 이유로 Aluminum 1xxx계 중심의 전자기 펄스 용접 공정이 연구되었다. 그러나 자동차 스페이스 프레임 및 드라이브 샤프트등과 같은 부품에 알루미늄재를 적용하기 위해서는 일정 강도를 확보할 수 있는 6xxx계의 관련 연구가 필요하다. 따라서 본 연구에서는 고품질의 접합부 확보를 위한 1xxx계와 6xxx의 최적의 공정변수(충전전압, 외부재와 내부재 사이의 간격, 외부재 두께)를 도출하였다. 이를 위하여 전자기 펄스 용접 장치는 한국생산기술연구원과 웰메이트(주)에서 공동으로 개발한 $120{\mu}F$의 캐패시터 6개로 구성된 'W-MPW36'을 사용하였으며 접합 후 누수시험을 통하여 접합부의 품질을 검토하였다.

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Implementation of an AMBA-Based IP for H.264 Transform and Quantization (H.264 변환 및 양자화 기능을 갖는 AMBA 기반 IP 구현)

  • Lee, Seon-Young;Cho, Kyeong-Soon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.10 s.352
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    • pp.126-133
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    • 2006
  • This paper describes an AMBA-based IP to perform forward and inverse transform and quantization required in the H.264 video compression standard. The transform and quantization circuit was optimized for area and performance. The AHB wrapper was added to the circuit for the AMBA-based operation. The user of the IP can specify how long the bus may be occupied by the IP and also where the video data are stored in the external memory. The function of the proposed IP based on AMBA Specification was verified on the platform board with Xilinx FPGA and ARM9 processor. We fabricated an MPW chip using $0.25{\mu}m$ standard cells and observed its correct operations on silicon.