Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design and MPW Implementation of 3D Graphics Floating Point Ips

3차원 그래픽용 부동 소수점 연산기 IP 설계 및 MPW 구현

  • Lee, Jung-Woo (Department of Electrical & Computer Engineering University of Seoul) ;
  • Kim, Ki-Chul (Department of Electrical & Computer Engineering University of Seoul)
  • 이정우 (서울시립대학교 전자전기컴퓨터공학부) ;
  • 김기철 (서울시립대학교 전자전기컴퓨터공학부)
  • Published : 2006.06.21
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Abstract

This paper presents a design and MPW implementation of 3D Graphics Floating Point IPs. Designed IPs include adder, subtractor, multiplier, divider, and reciprocal unit. The IPs have pipelined structures. The IPs meet the accuracy required in OpenGL ES. The operation frequency of the IPs is 100MHz. The IPs can be efficiently used in 3D graphics accelerators.

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