• 대한전기학회논문지
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• 제34권6호
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• pp.244-252
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• 1985

A model is presented to explain charging phenomena into the oxide layer when a metal-oxide-silicon(MOS) capacitor is driven by a large amplitude and high frequency ac signal sufficient to produce avalanche injection in the silicon. During avalanche, minority carriers are injected. It is assumed that some of these minority carriers attain sufficient energy to surmount the potential barrier at the interface, and then inter the oxide. Measurements of C-V curves are made for the MOS capacitor with p-type silicon substrates before and after avalanche injection. This paper studies how charging in the oxide and the interface depends on oxide properties. It is concluded that this charging effect is related to the presence of water in the oxide.

• 한국진공학회지
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• 제4권4호
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• pp.402-406
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• 1995

MOS(금속 산화막 반도체 접합) 소자가 방사선에 노출되면, 산화막재에 양의 공간전하가 생성되고 Si-SiO2 계면에 계면준위가 생성된다. MOS 커패시터의 방사선 조사효과를 방사선 피폭량과 산화막의 두께를 달리하는 시편에서 정전용량과 전류변화를 측정하여 고찰하였다. 정전용량-바이어스 전압 특성 실험결과로부터 플렛밴드 전압 및 계면상태밀도를 계산하였다. 또한 전압-전류 특성은 방사선 조사로 산화막내에 생성된 양의 공간전하와 Si-SiO2 계면에 포획된 전하에 의해서 설명이 가능하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.157-159
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• 2005

MOS capacitors were fabricated to study electrical and chemical properties of Ta-Mo metal alloy with $ZrO_2$. The work function of Ta-Mo alloy were varied from 4.1eV to 5.1eV by controlling the composition. When the atomic composition of Mo is 10%, good thermal stability up to $800^{\circ}C$ was observed and work function of MOS capacitor was 4.1eV, compatible for NMOS application. But pure Ta exhibited very poor thermal stability. After $600^{\circ}C$ annealing, equivalent oxide thickness of tantalum gate MOS capacitor was continuously decreased. Barrier heights of Ta-Mo alloy and pure metal that supported the work function values were calculated from Fowler-Nordheim analysis. As a result of these electrical?experiments, Ta-Mo metal alloy with $ZrO_2$ is excellent gate electrode for NMOS.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.788-791
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• 1988

The C-T characteristics of nitridized MOS capacitor have been studied. The generation lifetimes were calculated using C-T transient response ans found to vary as sample condition. This is due to the non-uniformity of fast surface state. Also, This experimental curves were different from theoretical curves. The result suggests that the change in material structure (from SiO2 to Si-N-O) is important in improving minority carrier lifetime.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.523-526
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• 2001

In this paper, we design and fabricate the high-efficiency and low-power switched-capacitor DC-DC converter. This converter consists of internal oscillator, output driver and output switches. The internal oscillator has 100kHz oscillation frequency and the output switches composed of one pMOS transistor and three nMOS transistors. According to the configuration of two external capacitors, the converter has three functions that are the Inverter, Doubler and Divider. The proposed converter is fabricated through the 0.8$\mu\textrm{m}$ 2-poly, 2-metal CMOS process. The simulation and experimental result for fabricated IC show that the proposed converter has the voltage conversion efficiency of 98% and power efficiency more than 95%.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.318.1-318.1
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• 2016

Hafnium Oxide (HfOx) has been attracted as a promising gate dielectric for replacing SiO2 in gate stack applications. In this paper, Metal-Oxide-Semiconductor (MOS) capacitor with solution processed HfO2 high-k material as a dielectric were fabricated. The solvent using $HfOCl2{\cdot}8H2O$ dissolve in 2-Methoxy ethanol was prepared at 0.3M. The HfOx layers were deposited on p-type silicon substrate by spin-coating at $250^{\circ}C$ for 5 minutes on a hot plate and repeated the same cycle for 5 times, followed by annealing process at 350, 450 and $550^{\circ}C$ for 2 hours. When the annealing temperature was increased from 350 to $550^{\circ}C$, capacitance value was increased from 337 to 367 pF. That was resulted from the higher temperature of HfOx which have more crystallization phase, therefore dielectric constant (k) was increased from 11 to 12. It leads to the formation of dense HfOx film and improve the ability of the insulator layer. We confirm that HfOx layer have a good performance for dielectric layer in MOS capacitors.

• 대한전자공학회논문지SD
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• 제48권5호
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• pp.18-24
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• 2011

DEM(Dynamic Element Matching) 기법중의 하나인 DWA(Data Weighted Averaging)는 멀티비트 Sigma-Delta Modulator에서 피드백 DAC의 단위요소 커패시터 부정합으로 인한 비선형성을 제거하기 위하여 널리 이용된다. 본 논문에서는 기존 DWA 구조에서 적용된 클록 타이밍을 조정하여 양자화기 데이터 코드 출력을 Latch 하는 $2^n$ Register 블록을 $2^n$ S-R latch 블록으로 대체하여 MOS Tr.를 줄임과 더불어 여분의 클록을 제거하였고, n-bit 데이터 코드를 지연시키기 위해 사용되는 2개의 n-비트 Register 블록을 1개의 n-비트 Register 블록으로 감소시켰다. 개선된 DWA 구조를 이용하여 3차 3-비트 SC(Switched Capacitor) Sigma-Delta Modulator를 설계한 후, 입력 주파수 20kHz, 샘플링 주파수 2.56MHz에서 0.1% DAC 단위 요소 커패시터 부정합을 갖도록 하여 시뮬레이션 한 결과 기존의 구조와 동일한 해상도를 얻을 수 있었고, 222개의 MOS Tr. 수를 줄일 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.130-131
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• 2005

In the era of submicron devices, super ultra thin gate oxide characteristics are required. Titanium silicide process has studied gate oxide reliability and dielectric strength characteristics as the composition of gate electrode. In this study the author observed process characteristics on MOS structure. In view point of the process characteristics of MOS capacitor, the oxygen & Ti, Si2 was analyzed by SIMS analysis on before and after annealing with 1,2 step silicidation, the Ti contents[Count/sec]of $9.5{\times}1018$ & $6.5{\times}1018$ on before and after 2'nd anneal. The oxygen contents[Count/sec] of $4.3{\times}104$ & $3.65{\times}104$, the Si contents[Count/sec] of $4.2{\times}104$ & $3.7{\times}104$ on before and after 2'nd anneal. The rms value[A] was 4.98, & 4.03 on before and after 2'nd anneal.

• 전자공학회논문지A
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• 제32A권7호
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• pp.58-68
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• 1995

Polysilicon capacitors with pyrogenic oxide and TEOX oxide as insulators were fabricated to develop capacitors which can be applied to analog CMOS IC, and the characteristics of the capacitors were compared with each other. The morphology of bottom polysilicon in pyrogenic oxide capacitor is degraded due to the generaged protuberances of the polysilicon grain during oxidataion. The polysilican capacitor with pyrogenic oxide of 57 nm thickness showed that the effective potential barrier height of 0.45 eV is much less than that of MOS capacitor (3.2 eV)when the top electrode is biased with a positive volgate. The morphology of the polysilicon capacitor with TEOS oxide, however, was not degraded during oxide deposition by LPCVD. The polysilicon capacitor with TEOS oxide of 54 nm thickness showed the effective potential barrier height of 1.28 eV when the top electrode is biased with a negative voltage. Therefore, it is concluded that the polysilicon capacitor with TEOS oxide is more applicable to analog CMOS IC than the pyrogenic oxide polysilicon capacitor.

• 한국전기전자재료학회논문지
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• 제27권9호
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• pp.547-550
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• 2014

In this study, the electrical characteristics of the nickel (Ni)/carbon nanotube (CNT)/$SiO_2$ structures were investigated in order to analyze the mechanism of CNT in MOS device structures. We fabricated 4H-SiC MOS capacitors with or without CNTs. CNT was dispersed by isopropyl alcohol. The capacitance-voltage (C-V) and current-voltage (I-V) are characterized. Both devices were measured by Keithley 4200 SCS. The experimental flatband voltage ($V_{FB}$) shift was positive. Near-interface trap charge density ($N_{it}$) and negative oxide trap charge density ($N_{ox}$) value of CNT embedded MOS capacitors was less than that values of reference samples. Also, the leakage current of CNT embedded MOS capacitors is higher than reference samples. It has been found that its oxide quality is related to charge carriers and/or defect states in the interface of MOS capacitors.