• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.2
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• pp.79-85
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• 2008

It is important to consider the life of battery and low power operation for various wireless communications. Thus, Analog current-mode signal processing with SI circuit has been taken notice of in designing the LSI for wireless communications. However, in current mode signal processsing, current memory circuit has a problem called clock-feedthrough. In this paper, we examine the connection of CMOS switch that is the common solution of clock-feedthrough and calculate the relation of width between CMOS switch for design methodology for improvement of current memory. As a result of simulation, when the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the width relation in CMOS switch is obtained with $W_{Mp}=5.62W_{Mn}+1.6$, for the nMOS width of 2~6um in CMOS switch. And from the same simulation condition, it is obtained with $W_{Mp}=2.05W_{Mn}+23$ for the nMOS width of 6~10um in CMOS switch. Then the defined width relation of MOS transistor will be useful guidance in design for improvement of current memory.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.35-41
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• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.12
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• pp.596-603
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• 2002

New layout methods for implementing MOS switches of ultra low channel resistance are presented. These area-effective layout methods include the waffle structure, zipper structure, star zag structure and fingered waffle structure. The design equations for these new layout structures are analyzed. The area-effectiveness of these structures is compared with that of the conventional alternating bar structure. MOS switches of the waffle structure were fabricated using a standard 0.25um CMOS process. The experimental characterization results of the fabricated MOS switches are presented. The analytical comparison and experimental results show that area reductions over 40% are achievable with the new structures.

• Proceedings of the KIEE Conference
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• 1991.11a
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• pp.231-233
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• 1991

This paper discribes a study on the switching character of MOS-GTO and the design of gate drive circuit. Chopping power supply converter, synchronious and asyncronious motor speed adjustment, inverter, etc., needs low drive energy "high frequency" switches. To fulfill these need, switches must have rapid switching time and insulated gate control. MOS-GTO structure is well suited to these constraints. The power switch is serial installation of a GTO thyrister and a MOS Transistor. The gate of the GTO is linked to positive pole of the cascode structure via a MOS high voltage transistor and ground via a transient absorber diode. This high performance MOS-GTO assembly considerably increases the strength which facilitate the drive of GTO thyristers.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.206-219
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• 1996

This paper describes a data structure and evaluation algorithm to improve the perofmrances MOS logic-with-timing simulation in computation and accuracy. In order to efficiently simulate the logic and timing of driver-load networks, (1) a tree data structure to represent the mutual interconnection topology of switches and nodes in the driver-lod network, and (2) an algebraic modeling to efficiently deal with the new represetnation, (3) an evaluation algorithm to compute the linear resistive and capacitive behavior with the new modeling of driver-load networks are developed. The higher modeling presented here supports the structural and functional compatibility with the linear switch-level to simulate the logic-with-timing of digital MOS circuits at a mixed-level. This research attempts to integrate the new approach into the existing simulator RSIM, which yield a mixed-klevel logic-with-timing simulator MIXIM. The experimental results show that (1) MIXIM is a far superior to RSIM in computation speed and timing accuracy; and notably (2) th etiming simulation for driver-load netowrks produces the accuracy ranged within 17% with respect ot the analog simulator SPICE.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.659-662
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• 1998

전자부품이나 설계된 회로시스템에 납땜을 하기 위해 인두를 사용하는데 누설전류, 서지전압, 정전기, 적절하지 못한 온도 등 여러 가지 악조건으로 인해 부품의 파괴를 가져온다. 특히 C-MOS로 설계된 소자의 경우는 다른 전자부품 보다 더 민감하기 때문에 파괴될 경우가 다발적으로 발생된다. 따라서 절연저항이 높고, 사용자가 적절한 온도로 제어할 수 있는 인두조절기 설계가 활발히 진행되고 있다. 본 논문에서는, 인두 히터에 센서를 삽입하여 이 저항의 변화율에 따라 온도를 감지하고, 주파수 방해를 최소화할 수 있는 Zero Voltage Switch IC를 사용하여 히터의 온도를 제어하였다. 또한, 사용자가 온도 변화를 알 수 있도록 A/D 변환기를 사용하여 시그먼트로 표시하였다. 기존에 설계된 시스템은 온도를 감지하는 센서가 민감하며 센서에서 감지된 신호가 비교기를 통해서 직접 히터의 온도를 제어하였기 때문에 온도 변화율이 매우 심하고, 이두팁이 분리되어있지 않기 때문에 절연저항이 매우 낮았다. 본 논문에서는, 이러한 문제점을 해결하기 위해 센서의 민감성을 최소화하고, Zero Voltage Switch IC를 사용하여 히터의 온도를 정밀하게 제어하였으며, 절연저항을 높이기 위해 인두팁의 중간에 세라믹을 삽입하여 팁에 온도만 전달될 수 있도록 용접을 하여 기존의 문제점을 개선하였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.6
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• pp.700-709
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• 1988

A new technique is proposed for switch-level logic simulation for NMOS and CMOS logic circuits. For the simple inverter the rise or fall delay time is approximated by a product of polynomials of the input waveform slope, the output loading capacitance and the device configuration ratio, the polynomial coefficients being so determined as to best fit the SPICE simuladtion results for a given fabrication process. This approach can easily and accurately be extened to the case of multiple input transitions. The simulation results show that proposed method can predict the delay times within 5% error and with a speed up by a factor of three orders of magnitude for several circuits tested, as compared with the SPICE simulation.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2008.04a
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• pp.247-250
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• 2008

최근 무선통신용 LSI는 배터리 수명과 관련하여, 저전력 동작이 중요시되고 있다. 따라서 Digital CMOS 신호처리와 더불어 동작 가능한 SI (Switched-Current) circuit를 이용하는 Current-mode 신호처리가 주목받고 있다. 그러나 SI circuit의 기본인 Current Memory는 Charge Injection에 의한 Clock Feedthrough라는 문제점을 갖고 있기 때문에, 전류 전달에 있어서 오차를 발생시킨다. 본 논문에서는 Current Memory의 문제점인 Clock Feedthrough의 해결방안으로 CMOS Switch의 연결을 검토하였고, 0.25${\mu}m$ CMOS process에서 Memory MOS와 CMOS Switch의 Width의 관계는 simulation 결과를 통하여 확인하였으며, MOS transistor의 관계를 분명히 하여, 설게의 지침을 제공한다.

• Journal of Internet of Things and Convergence
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• v.6 no.1
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• pp.97-102
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• 2020

Multi-Channel Switch ICs for IoT have integrated several solid state structure low ON-resistance bi-directional relay MOS switches with level shifter to drive high voltage and they should be independently controlled by external serialized logic control. These devices are designed for using in applications requiring high-voltage switching control by low-voltage control signals, such as medical ultra-sound imaging, ink-jet printer control, bare board open/short and leakage test system using Kelvin 4-terminal measurement method. This paper describes implementation of analog switch control block and its verification using Field programmable Gate Array (FPGA) test pattern generation. Each block has been implemented using Verilog hardware description language then simulated by Modelsim and prototyped in a FPGA board. Compare to conventional IC, The proposed architecture can be applied to fields where multiple entities need to be controlled simultaneously in the IoT environment and the proposed pattern generation method can be applied to test similar types of ICs.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.2
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• pp.159-164
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• 2016

A wireless communication system is required to be implemented with the low power circuits because it uses a battery having a limited energy. Therefore, the current mode circuit has been studied because it consumes constant power regardless of the frequency change. However, the clock-feedthrough problem is happened by leak of stored energy in memory operation. In this paper, we suggest the current memory circuit to minimize the clock-feedthrough problem and introduce a technique for ultra low power operation by inducing dynamic voltage scaling. The current memory circuit was designed with BSIM3 model of $0.35{\mu}m$ process and was operated in the near-threshold region. From the simulation result, the clock-feedthrough could be minimized when designing the memory MOS Width of $2{\mu}m$, the switch MOS Width of $0.3{\mu}m$ and dummy MOS Width of $13{\mu}m$ in 1MHz switching operation. The power consumption was calculated with $3.7{\mu}W$ at the supply voltage of 1.2 V, near-threshold voltage.