• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1717-1723
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• 2007

In this study , quasi-MFISFET (Metal-Ferroelectric-Insulator-Semiconductor FET) devices are fabricated using PLZT(10/30/70), PLT(10), PZT(30/70) thin film and their drain current properties are investigated. It is found that the drain current of quasi-MFISFET is directly influenced by the polarization strength of ferroelectric thin fan. Also, when the gate voltages are ${\pm}5\;and\;{\pm}10V$, the memory windows are 0.5 and 1.3V, respectively. It means that the memory window is changed with the variation of coercive voltage generated by the voltage applied on ferroelectric thin film. The electric field and the leakage current with time delay of PLZT(10/30/70) thin lam are measured to investigate the retention property of MFISFET device. Some material parameters such as current density constant, $J_{ETO}$, electric field dependent factor K and time dependent factor m are obtained. The variation of charge density with time is quantitatively analyzed by using the material parameters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.166-173
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• 2001

Hysteresis loops of the ferroelectric thin films such as PLZT(10/30/70), PLT(10) and PZT(30/70) was simulated using the field-dependent polarization model and compared to the measured loops. In case of PZT(30/70) thin film, as the real saturation or polarization at the applied voltage or larger than 5V appears slack and its value is quite different from the simulated one, it is deduced that the ferroelectric polarization of PZT(30/70) is generated not only by the pure dipoles but also by various electric charges. The drain current of quasi-MFISFET is expressed by using the square-law FET and field-dependent polarization models. The modeling results are analogous to the experimental values. The channel of quasi-MFISFET using PZT(30/70) forms more quickly compared to that of quasi-MFISFET using PLZT(10/30/70) or PLT(10) in the state of 'write' gate voltage of -10V. This may be because the decrease rate of the polarization in the PZT(30/70) thin film is 3~4 times more rapid than that of the polarization in the PLZT(10/30/70) or the PLT(10) thin film in the retention characteristics.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.1 s.34
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• pp.59-63
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• 2005

A simulation method combined with the simulation program with integrated circuit emphasis (SPICE) and the technology computer-aided design (TCAD) has been proposed to estimate the electrical characteristics of the metal-ferroelectric-semiconductor field effect transistor (MFS/MFISFET). The complex behavior of the ferroelectric property was analyzed and surface potential of the channel region in the MFS gate structure was calculated with the numerical TCAD method. Since the calculated surface potential is equivalent with the surface potential obtained with the SPICE model of the conventional MOSFET, we can obtain the current-voltage characteristics of MFS/MFISFET corresponding to the applied gate bias. Therefore, the proposed method will be very useful for the design of the integrated circuits with MFS/MFISFET memory cell devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.12-12
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• 2001

PLZT(10/30/70), PLT(10) 및 PZT(30/70) 와 같은 강유전체 박막의 이력곡선을 field-dependent polarization 모델을 이용하여 시뮬레이션하고, 측정한 실험적 결과와 비교, 분석하였다. PZT(30/70) 박막의 경우, 5V 이상의 인가전압에서 분극의 포화현상이 둔감하게 나타나고 시뮬레이션 값과의 차이도 심해 강유전체 분극이 순수한 dipole 외에도 다양한 전하의 영향을 받아 형성된다는 사실을 알 수 있다. 또, quasi-MFISFET 소자의 드레인 전류는 field-dependent polarization 모델의 강유전체 이력곡선에서 얻은 파라미터를 square-law FET 모델에 적용시켜 효과적으로 추출하였고, 모델링 결과는 실험값과 유사하였다. 그리고, quasi-MFISFET 소자의 gate 에 -10V의 ′write′ 전압을 인가한 상태에서 PZT(30/70) 박막을 사용한 경우, PLZT(10/30/70), PLT(10) 박막 보다 빨리 채널이 형성되었는데, 그 원인은 강유전체 박막에 따른 retention 특성에서 PZT(30/70) 박막의 분극 감소가 PLZT(10/30/70), PLT(10) 박막의 분극 감소 보다 약 3∼4 배 이상 크다는 점에서 찾을 수 있다.

• Proceedings of the Materials Research Society of Korea Conference
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• 1999.05a
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• pp.27-27
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• 1999

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.2
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• pp.135-139
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• 2008

MFISFETs with platinum electrode on the $LiNbO_3$/aluminum nitride/Si(100) structures were successfully fabricated and the properties of the FETs have been discussed. $I_D-V_G$ characteristics of MFISFETs for linear region (that is, 0.1 V of the drain voltage) showed hysteresis loop with a counter-clockwise trace due to the ferroelectric nature of $LiNbO_3$ films. A memory window (i.e., threshold voltage shift) of the fabricated device was about 2[V] for a sweep from -4 to +4[V]. The estimated field-effect electron mobility and transconductance on a linear region were 530[$cm^2/V{\cdot}s$] and 0.16[mS/mm], respectively. The drain current of 27[${\mu}A$] on the "on" state was more than 3 orders of magnitude larger than that of 30[nA] on the "off" state at the same "read" gate voltage of l.5[V], which means the memory operation of the MFISFET.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.5
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• pp.383-387
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• 2002

N-channel metal-ferroelectric-insulator-semiconductor field-effect-transistors (MFISFET's) by using $SrBi_2Ta_2O_9$/Silicon Nitride/Si (100) structure were fabricated. The fabricated devices exhibit comfortable memory windows, fast switching speeds, good fatigue resistances, and long retention times that are suitable for advanced ferroelectric memory applications. The estimated switching time and polarization ($2P_r$) of the fabricated FET measured at applied electric field of 376 kV/cm were less than 50 ns and about 1.5 uC/$\textrm{cm}^2$, respectively. The magnitude of on/off ratio indicating the stored information performance was maintained more than 3 orders until 3 days at room temperature. The $I_DV_G$ characteristics before and after being subjected to $10^11$ cycles of fatigue at a frequency of 1 MHz remained almost the same except a little distortion in off state.

• Korean Journal of Materials Research
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• v.10 no.12
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• pp.807-811
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• 2000

CeO$_2$ and SrBi$_2$Ta$_2$O$_{9}$ (SBT) thin films for MFISFET (Metal-ferroelectric-insulator-semiconductor-field effect transistor) were deposited by r.f. sputtering and pulsed laser ablation method, respectively. The effects of sputtering gas ratio(Ar:O$_2$) during deposition for CeO$_2$ films were investigated. The CeO$_2$ thin films deposited on Si(100) substrate at $600^{\circ}C$ exhibited (200) preferred orientation. The preferred orientation, Brain size and surface roughness of films decreased with increasing oxygen to argon gas ratio. The films deposited under the condition of Ar:O$_2$= 1 : 1 showed the best C- V characteristics. The leakage current of films showed the order of 10$^{-7}$ ~10$^{-8}$ A at 100kV/cm. The SBT thin films on CeO$_2$/Si substrate showed dense microstructure of polycrystalline phase. From the C-V characteristics of MFIS structure with SBT film annealed at 80$0^{\circ}C$, the memory window width was 0.9V at 5V The leakage current density of Pt/SBT/CeO$_2$/Si structure annealed at 80$0^{\circ}C$ was 4$\times$10$^{-7}$ /$\textrm{cm}^2$ at 5V.

• Proceedings of the Materials Research Society of Korea Conference
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• 1999.11a
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• pp.72-72
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• 1999

• Transactions on Electrical and Electronic Materials
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• v.1 no.1
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• pp.40-44
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• 2000

Metal-ferroelectric-insulator-semoiconductor field effect transistor (MFISFETs) were fabricated using CMOS processes. The Pt/SBT/NO combined layers were etched for forming a conformal gate by using Ti/Cr metal masks and a two step etching method, By the method, we were able to fabricate a small-sized gate with the dimension of $16/4{\mu}textrm{m}$ in the width/length of gate. It has been chosen the non-self aligned source and drain implantation process, We have deposited inter-layer dielectrics(ILD) by low pressure chemical vapor deposition(LPCVD) at $380^{circ}C$ after etching the gate structure and the threshold voltage of p-channel MFISFETs were about 1.0 and -2.1V, respectively. It was also observed that the current difference between the $I_{ON}$(on current) and $I_{OFF}$(off current) that is very important in sensing margin, is more that 100 times in $I_{D}-V_{G}$ hysteresis curve.