• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.8
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• pp.816-823
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• 2008

This paper describes the test results of developed high speed data processing unit using Xilinx GTP(Multi-Gigabit-Transceiver) interface and DDR-2 memory. The high speed data processing unit receives input data from packet generator at 1.25Gbps and transmits stored data to the data receiving system at 700Mbps. Therefore, DDR-2 memory controller and Xilinx GTP interface are implemented by FPGA instead of CPU to process high speed data directly.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.2
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• pp.195-201
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• 2008

This paper compares the performance of Mass Memory Unit(MMU) between Science and Technology Satellite 1(STSAT-1) and STSAT-2 from developed Proto Flight Model(PFM) for Miniaturization, lightweight and low power consumption. MMU receives the payload data at 200Kbps and transmits them to XTX at 10Mbps in the STSAT-2. The performance of PFM MMU in the Functional and space environments test satisfies the requirements of STSAT-2.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.10
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• pp.1026-1031
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• 2008

This paper describes the establishment result of high speed data receiving and archiving system(HDRAS) using data receiving card(DRC) developped by SaTReC and low cost RAID(Redundant Array of Independent Disks) storage instead of expensive enterprise RAID storage. We used three S-ATA2 type hard disks and performance test program developped by SaTReC to receive and save data at 350Mbps. Finally, we verified that the HDRAS using low cost RAID storage has a capacity to process received data at 79MB/s(632Mbps).

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.9
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• pp.1770-1776
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• 2011

In this study, a new method that can estimate ICG data from a subject's both hands to measure Cardiac Output under convenient sensor environment. With this aim, a grip-type electrode was implemented to measure ICG. To improve the accuracy of measurement, the regression equation was extracted using multiple bio-parameters and our result was compared with the thoracic ICG equipment(Physio Flow$^{(R)}$, PF104D, Manatec Biomedical, France), which is being used in clinics. The subjects consist of 26 men and 4 women(age in $22.0{\pm}3.32$). They are no cardiac disease. Parameters available for regression model were used gender, BMI, MBP, LVET, dZ/dt(max), distance between the measured electrodes, body impedance, and PTT. As a result of analyzing the ICG measurement value on thorax and both hands, the correlation with stroke volume, heart rate, and cardiac output was $R^2$=0.853, $R^2$=0.958 and $R^2$=0.899, respectively.

• 한국정보통신설비학회:학술대회논문집
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• 2002.08a
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• pp.85-104
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• 2002

최근 정부(정보통신부)는 사이버 아파트를 포함하여 초고속 정보통신망을 2005년까지 구축하여 각 가정당 10Mbps의 고속 정보통신서비스를 실현한다는 계획을 발표하고, 초고속 정보통신을 활성화하므로 정보통신 선진국 진입을 위하여 "초고속 정보통신 건물 인증제도"를 발표, 현재 시행하고 있다. (1999.7 제정발표) 그러나 시행 과정에서 아파트 중앙 관리실에 있는 MDF 이후의 광케이블과 기타 공사는 건설회사에서 시공하고 중앙 관리실 MDF 이전의 광케이블 공사와 중앙관리실 LAN시설 등의 공사는 통신 전문업체로 하여금, 입주자 별도 부담금으로 시공하고 있다. (컨소시엄구성) 최근 아파트 분양열기 고조로 건설회사 마다 "초고속 정보통신아파트"인증 1등급이라고 선전 및 분양광고 중인데 실제는 "1등급"이 아니고 "2등급" 또는 "3등급"인 경우가 있어, 정부가 목표하는 각 가정당 10Mbps, 개인당 2Mbps 고속정보통신 서비스는 실현성 문제점이 있다. 정부의 인증심사 기준에 중앙관리실 장비 등에 대한 것은 심사기준에 누락되어 있고 또 사생활 정보보호를 위한 대응기술, 시스템 준비 정도까지 포함하여 종합적으로 평가한 뒤 인증을 부여하여야 한다는 것이 본인의 연구 초점이다. 사이버 아파트란 광통신을 주축으로 영상과 음성, 데이터를 자유 자재로 전송 처리하는 초고속 정보통신망을 이용하는 것으로 LAN 장비를 이용하여 각 세대간 통신은 물론 누구나 인터넷을 사용할 수 있는 기능이 있는 설계된 아파트를 말한다. 사이버 아파트의 네트워크에는 금융, 홈쇼핑, 예약, 지역정보, 관공서, 의료서비스, 레저 생활정보 등 차별화된 콘텐츠 확보가 필요하다. 본 연구의 핵심은 사이버 아파트의 현 실태와 문제점, 정부의 인증심사 기준의 미비점과 문제점, 사이버 아파트의 기능, 구성요소, 시스템 구축, 서버활용도, 장비들에 관한 것과 그리고 정부의 사이버 아파트 육성정책, 정보보호 대책과 관련업체들의 동향 등을 연구하여 요약 정리하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.1
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• pp.61-66
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• 2001

In this paper, we design high speed Viterbi decoding algorithm which is aimed for Wireless LAN. Wireless LAN transmits data at rate 6∼54 Mbps. This high speed is not easy to implement Viterbi decoder with single ACS. So parallel ACS butterfly structure is to be used and several time-dependent problem is to be solved. We simulate Viterbi algorithm using new branch metric calculating method to save time, and consider trace back algorithm which is adaptable to high speed Viterbi decoder. With simulated, we determine the structure of Viterbi decoder. This architecture is available to high speed and low power Viterbi decoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3B
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• pp.85-94
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• 2005

In this paper, we propose a reliable high-speed UDP-based media transport with an adaptive error control. The proposed adaptive transport scheme controls the amount of redundancy by monitoring the network in order to adapt to network fluctuations efficiently. The feedback of receiver enables the sender to be aware of current reception status (i.e., rate and type of packet loss) and to estimate the expected network status. Based on this, the proposed transport attempts to enable reliable transport by adaptively controlling the amount of both whole sending rate and the ratio for adaptive FEC code. Experiment with high-speed network has been conducted to verify the performance of the proposed system that demonstrates the enhanced reliability of the proposed transport at the speed of up to several hundred Mbps.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.4
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• pp.389-394
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• 2010

This paper describes the conceptual design of mass memory unit for high speed data processing and mass memory management in the STSAT-3 compared to that of STSAT-2. The FPGA directly controls the data receiving from two payloads with the maximum 100Mbps speed and 32Gb mass memory management to satisfy these requirements. We used SRAM-based FPGA from XILINX having fast operating speed and large logic cells. Therefore, the Triple Modular Redundancy(TMR) and configuration memory scrubbing techniques will also be used to protect FPGA from Single Event Upset(SEU) in space.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.77-84
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• 2000

In this paper, we discuss a symbol clock extraction scheme based on maximizing the band-edge component of the transmitted signal frequency spectrum for applications to 51.84Mbps VDSL system which uses a 16-QAM. The major characteristics of the digital PLL are examined. In addition, we suggest an efficient design method of a sinusoidal look-up table which is used for NCO.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.84-89
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• 2007

In order to design and test an SoC modem for high speed communication, the platform with the architecture of such high speed communication is needed. That platform is needed for testing large data in speed of 500Mbps. This paper shows that transmission data can be uploaded and downloaded by 250Mbps between a virtual modem target board and a PC through the AHB-PCI IP and the speed of based on DPRAM and PCI.