• 디지털콘텐츠학회 논문지
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• 제15권3호
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• pp.433-438
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• 2014

본 논문은 배터리와 태스크를 고려한 저전력 알고리듬을 제안하였다. 제안한 알고리듬은 배터리의 용량과 사용 목표 시간에 따른 단위 시간의 소모 전력을 설정한다. 주어진 모든 태스크들의 소모 전력을 계산한다. 태스크들 중에서 소모 전력이 가장 큰 태스크의 소모 전력과 소모 전력이 가장 작은 태스크의 소모 전력의 평균을 구한다. 태스크의 소모 전력의 평균을 단위 시간을 고려하여 다시 소모 전력을 계산한다. 태스크의 평균 소모 전력의 크기가 계산된 소모 전력의 평균보다 작거나 같을 경우 태스크의 평균 소모 전력보다 큰 태스크 들을 대상으로 저전력을 수행한다. 또한, 태스크의 평균 소모 전력의 크기가 계산된 소모 전력의 평균보다 클 경우 계산된 소모 전력의 평균보다 큰 태스크 들을 대상으로 저전력을 수행한다. 저전력은 태스크의 프로세서와 디바이스의 소모 전력을 분할하여 소모 전력이 큰 부분에 대해 저전력을 수행한다. 실험은 배터리를 고려한 저전력 알고리듬인 [6]과 비교하였다. 실험결과 [6]보다 소모 전력이 감소되어 알고리듬의 효율성이 입증되었다.

• 디지털콘텐츠학회 논문지
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• 제14권1호
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• pp.59-64
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• 2013

본 논문에서는 태스크에 따른 저전력 알고리즘을 제안하였다. 태스크는 시스템의 작업 수행에 필요한 프로세서의 내부와 외부의 자원을 의미한다. 태스크에 따라 저전력 회로를 구현하기 위해서는 각각의 태스크에 대한 생존시간과 호출횟수를 분석한다. 회로 전체의 소모 전력을 감소하기위해서는 소모 전력이 가장 높은 태스크의 소모 전력을 우선 줄여 저전력 회로를 구현할 수 있다. 따라서 소모 전력이 최대인 태스크를 우선 선별하여야 한다. 소모 전력이 최대인 태스크는 태스크의 생존시간과 호출횟수를 고려하여 순위를 선정한다. 태스크의 생존시간이 길면서 호출횟수가 많은 태스크의 경우 가장 큰 소모 전력을 발생시키는 태스크이므로 소모 전력을 감소시킬 최우선 순위가 된다. 소모 전력이 최대인 태스크로부터 생존 시간과 호출횟수를 이용하여 저전력 회로로 구현하기 위한 주파수를 결정하여 회로 전체의 소모 전력을 감소시킨다. 또한, 생존 시작 시간에서 생존 마지막 시간까지 계속해서 최소의 소모 전력으로 태스크를 유지시켜 전체 소모 전력을 감소시킨다. 실험 결과 [7] 알고리즘에 비해 5.43%의 전력 소모가 감소된 결과를 나타내었다.

• 디지털산업정보학회논문지
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• 제9권1호
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• pp.53-58
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• 2013

In this paper, we proposed low power algorithm for battery residual capacity and a task. Algorithm the mobile devices power of the battery residual capacity for the task to perform power consumption to reduce the frequency alters. Task is different in power consumption according to kinds of in time accomplishment device to use. Adjustment of power consumption analyzes kinds of given tasks from having the minimum power consumption task to having the maximum power consumption task. Control frequency so that power consumption waste to be exposed to battery residual capacity can be happened according to the results analyzed. Experiment the frequency by adjusting power consumption a method to reduce using [7] and in the same environment power of the battery residual capacity consider the task to perform frequency were controlled. Efficiency was proved compare with the experiment results [7]. The experiments results show increment in the number of processing by 45.46% comparing with that [7] algorithm.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
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• pp.231-233
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• 2005

For the low-power design of the mobile multimedia system architecture, this paper modeling the mobile multimedia system and analysis the power consumption profile about the whole communication environment. The mobile system model consist of air interface, RIP front-end, base-band processing module and human interface. For the result of power consumption profile analysis, the power consumption of multimedia processing is above 60% compare to the whole power consumption in mobile multimedia system. To minimize the power consumption in processing module which consumes the large power, this paper proposed the Microscopic DVS technique which applies the optimum voltage for the each multimedia frame. For the simulation result, proposed power minimization technique reduce the power consumption about 30%.

• 전자통신동향분석
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• 제35권2호
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• pp.69-78
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• 2020

Small portable devices such as mobile phones and laptops currently display a trend of high power consumption owing to their characteristics of high speed and multifunctionality. Low-power SoC design is one of the important factors that must be considered to increase portable time at limited battery capacities. Popular low power SoC design techniques include clock gating, multi-threshold voltage, power gating, and multi-voltage design. With a decreasing semiconductor process technology size, leakage power can surpass dynamic power in total power consumption; therefore, appropriate low-power SoC design techniques must be combined to reduce power consumption to meet the power specifications. This study examines several low-power SoC design trends that reduce semiconductor SoC dynamic and static power using EDA tools. Low-power SoC design technology can be a competitive advantage, especially in the IoT and AI edge environments, where power usage is typically limited.

• 디지털산업정보학회논문지
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• 제5권3호
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• pp.69-75
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• 2009

In this paper, we proposed CPLD low power algorithm using reduce glitch power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within CPLD. Glitch removal process using delay buffer insertion method for feasible cluster. Also, glitch removal process using same method between feasible clusters. The proposed method is examined by using benchmarks in SIS, it compared power consumption to a CLB-based CPLD low power technology mapping algorithm for trade-off and a low power circuit design using selective glitch removal method. The experiments results show reduction in the power consumption by 15% comparing with that of and 6% comparing with that of.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.79-82
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• 2003

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to $V_{ref}-V_{TH}$, where $V_{ref}=V_{DD}-nV_{TH}$. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we propose a low-power $4\times4$ bit parallel multiplier. The proposed circuits are simulated with HSPICE under $0.35{\mu}m$ CMOS standard technology. Compare to the previous works, this circuit can reduce the power consumption rate of 11.2% and the power-delay product of 10.3%.

• Journal of Information Processing Systems
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• 제9권1호
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• pp.41-52
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• 2013

One of the obstacles preventing the Zigbee protocol from being widely used is the excessive power consumption of Zigbee devices in low bandwidth and low power requirement applications. This paper proposes a protocol that resolves the power efficiency problem. The proposed protocol reduces the power consumption of Zigbee devices in beacon-enabled networks without increasing the time taken by Zigbee peripherals to communicate with their coordinator. The proposed protocol utilizes a beacon control mechanism called a "sleep pattern," which is updated based on the previous event statistics. It determines exactly when Zigbee peripherals wake up or sleep. A simulation of the proposed protocol using realistic parameters and an experiment using commercial products yielded similar results, demonstrating that the protocol may be a solution to reduce the power consumption of Zigbee devices.

• 대한임베디드공학회논문지
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• 제10권2호
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• pp.91-99
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• 2015

The electric power consumed by the embedded devices has become a critical issue because the reduction of power consumption is an important factor to prolong the battery-operated devices' lifetime. Many researches and techniques to reduce the power consumption have been proposed and developed but any power method cannot guarantee optimal power consumption of an embedded device - it would be faced with numerous situation - in all ways. Specifically, power researches for embedded devices deployed in the industry field have hardly been done. In this paper, low power service is proposed to minimize power reduction with the several usage status of embedded devices in the industry field. The usage status is basically classified according to the distance between the device and the user which is obtained by the ultrasonic and PIR sensor. The performance evaluation shows that the proposed scheme can reduce the power consumption by up to 45.3% compared to the device with no power reduction scheme. It also shows that the power consumption of the proposed scheme is 5.2% ~ 16.8% lower than that of the timeout scheme.

• 전기학회논문지
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• 제58권11호
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• pp.2281-2285
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• 2009

Powerline communication is the data signal which is modulated by carrier frequency through the installed powerline at in-home or office is transmitted and received signals are separated into data signal with using band-pass filter which cent-frequency is carrier frequency. The home gateway, an equipment which works as an gateway for ubiquitous home network, relays all functions of a home network. The home gateway must always be connected in order to provide seamless services. However it gives unfavorable power consumption. Therefore the needs for working in maximum power saving mode while there is no data traffic and for invoking to the normal function when it is necessary. So, in this paper we survey the development of low power PLC modem monitoring of power consumption and breaking abnormal power in the home Network.