• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.12
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• pp.2300-2307
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• 2008

This study receives the noise transmitted in a constant audio frequency range through a microphone array in which the noise(like grease in a pan) occurs on the power supply line due to the troublesome partial discharge(arc). Then by going through a series of signal processing of removing noise, this study measures the distance and direction up to the noise caused by the troublesome partial discharge(arc) and monitors the result by displaying in the analog and digital method. After these, it determines the state of each size and judges the distance and direction of problematic part. When the signal sound transmitted by the signal source of bad insulator is received on each microphone, the signal comes only in the frequency range of 20 kHz by passing through the circuit of amplification and 6th low pass filter. Then, this signal is entered in a digital value of digital signal processing(TMS320F2812) through the 16-bit A/D conversion. By doing so, the sound distance, direction and coordinate of bad insulator can be detected by realizing the correlation method of detecting the arriving time difference occurring on each microphone and the algorithm of detecting maximum time difference.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1776-1782
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• 2010

The interferometric fiber optic gyroscopes (FOGs) are well known as sensors of rotation, which are based on Sagnac effect, and have been under development for a number of years to meet a wide range of performance requirements. This paper describes the development of open-loop FOG and digital signal processing techniques implemented on FPGA. Our primary goal was to obtain intermediate accuracy (pointing grade) with a good bias stability (0.22deg) and scale factor stability, extremely low angle random walk (0.07deg) and significant cost savings by using a single mode fiber. A secondary goal is to design all digital FOG signal processing algorithms with which the SNR at the digital demodulator output is enhanced substantially due to processing gain. The Cascaded integrator bomb(CIC) type of decimation filter only requires adders and shift registers, low cost processors which has low computing power still can used in this all digital FOG processor.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.2
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• pp.79-85
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• 2008

It is important to consider the life of battery and low power operation for various wireless communications. Thus, Analog current-mode signal processing with SI circuit has been taken notice of in designing the LSI for wireless communications. However, in current mode signal processsing, current memory circuit has a problem called clock-feedthrough. In this paper, we examine the connection of CMOS switch that is the common solution of clock-feedthrough and calculate the relation of width between CMOS switch for design methodology for improvement of current memory. As a result of simulation, when the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the width relation in CMOS switch is obtained with $W_{Mp}=5.62W_{Mn}+1.6$, for the nMOS width of 2~6um in CMOS switch. And from the same simulation condition, it is obtained with $W_{Mp}=2.05W_{Mn}+23$ for the nMOS width of 6~10um in CMOS switch. Then the defined width relation of MOS transistor will be useful guidance in design for improvement of current memory.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.10
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• pp.2883-2902
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• 2023

Since the existing anti-jamming methods, including intelligent methods, have difficulty against high-speed reactive jamming, we studied a new methodology for jamming utilization instead of avoiding jamming. Different from the existing jamming utilization techniques that harvest energy from the jamming signal as a power supply, our proposed method can take the jamming signal as a favorable factor for frequency detection. Specifically, we design an intelligent differential frequency hopping communication framework (IDFH), which contains two stages of training and communication. We first adopt supervised learning to get the jamming rule during the training stage when the synchronizing sequence is sent. And then, we utilize the jamming rule to improve the frequency detection during the communication stage when the real payload is sent. Simulation results show that the proposed method successfully combated high-speed reactive jamming with different parameters. And the communication performance increases as the power of the jamming signal increase, hence the jamming signal can help users communicate in a low signal-to-noise ratio (SNR) environment.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.310-318
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• 2016

Emerging technologies such as the Internet of Things (IoT) and the Advanced Driver Assistant System (ADAS) often have image transmission functions with tough constraints, like low power and/or low delay, which require that they adopt line-based, low memory compression methods instead of existing frame-based image compression standards. Bit rate control in the conventional frame-based compression systems requires a lot of hardware resources when the scope of handled data falls at the frame level. On the other hand, attempts to reduce the heavy hardware resource requirement by focusing on line-level processing yield uneven image quality through the frame. In this paper, we propose a bit rate control that maintains consistency in image quality through the frame and improves the legibility of text regions. To find the line characteristics, the proposed bit rate control tests each line for ease of compression and the existence of text. Experiments on the proposed bit rate control show peak signal-to-noise ratios (PSNRs) similar to those of conventional bit rate controls, but with the use of significantly fewer hardware resources.

• Journal of Satellite, Information and Communications
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• v.8 no.3
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• pp.10-14
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• 2013

In this paper, when applying current-mode circuit design technique showing constant power dissipation none the less operation frequency, to the low power design of dynamic voltage frequency scaling, we introduce the low power current-mode circuit design technique applying MOSFET in sub-threshold region, in order to solve the problem that has large power dissipation especially on the condition of low operating frequency. BSIM 3, was used as a MOSFET model in circuit simulation. From the simulation result, the power dissipation of the current memory circuit with sub-threshold MOSFET showed $18.98{\mu}W$, which means the consumption reduction effect of 98%, compared with $900{\mu}W$ in that with strong inversion. It is confirmed that the proposed circuit design technique will be available in DVFS using a current-mode circuit design.

• Journal of the Institute of Convergence Signal Processing
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• v.19 no.3
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• pp.89-96
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• 2018

This study aims to develop a fully passive smart sensing tag utilizing RF (Radio Frequency) energy harvesting technology at UHF (Ultra High Frequency) band of 915MHz. To optimize the power collected under various radiated conditions, an efficient energy harvesting module exploiting a boost circuit with maximum power point tracking (MPPT) is employed. Specifically, the proposed tag features two orthogonal antennas to enhance its capability of both energy scavenging and data transmissions. The experimental result shows that the developed smart sensor tag can scavenge an RF input power of as low as 0.19mW at a distance of 4 meters for a 3.6Vdc output. Furthermore, the proposed smart sensor tag performs the feasibility of completely autonomous monitoring food freshness at 2 meters with a low-power sensor array.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.11
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• pp.3761-3779
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• 2022

The performance of existing recognition algorithms for binary phase shift keying (BPSK) and quadrature phase shift keying (QPSK) signals degrade under conditions of low signal-to-noise ratios (SNR). Hence, a novel recognition algorithm based on features in the graph domain is proposed in this study. First, the power spectrum of the squared candidate signal is truncated by a rectangular window. Thereafter, the graph representation of the truncated spectrum is obtained via normalization, quantization, and edge construction. Based on the analysis of the connectivity difference of the graphs under different hypotheses, the sum of degree (SD) of the graphs is utilized as a discriminate feature to classify BPSK and QPSK signals. Moreover, we prove that the SD is a Schur-concave function with respect to the probability vector of the vertices (PVV). Extensive simulations confirm the effectiveness of the proposed algorithm, and its superiority to the listed model-driven-based (MDB) algorithms in terms of recognition performance under low SNRs and computational complexity. As it is confirmed that the proposed method reduces the computational complexity of existing graph-based algorithms, it can be applied in modulation recognition of radar or communication signals in real-time processing, and does not require any prior knowledge about the training sets, channel coefficients, or noise power.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.5
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• pp.267-270
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• 2014

This paper presents the comparative performance of an adaptive FIR filter for a Delayed LMS algorithm. The delayed error signal was used to obtain a Delayed LMS algorithm to allow efficient pipelining for achieving a small critical path and area efficient implementation. This paper presents hardware efficient results (device utilization parameters) and power consumed. The FPGA families (Artix-7, Virtex-7, and Kintex-7) for a low voltage perspective are shown. The synthesis results showed that the artix-7 CMOS family achieves the lowest power consumption of 1.118 mW with 83.18 % device utilization. Different Precision strategies, such as the speed optimization and power optimization, were imposed to achieve these results. The algorithm was implemented using MATLAB (2013b) and synthesized on the Leonardo spectrum.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.321-324
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• 2001

This paper describes a fast and low-power multiplier co-processor architecture for digital signal processing applications and real-time control systems and its use as a multiplier co-processor for a 32-bit RISC microprocessor utilizing its one of the 16 co-processor interfaces. Its architecture adopts various algorithms to reduce the dynamic power and the area as well. The designed multiplier performs 32$\times$32 bit multiplication, and was designed using verilog HDL and 0.35${\mu}{\textrm}{m}$, 3V, 4M CMOS standard cell library. Its target operating speed is 40MHz, area lower than 10000 gate counts, and 10mW/MHz of power.