• 전자공학회논문지B
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• 제31B권7호
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(5)
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• pp.47-50
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• 2001

Nowadays ARM7 core is used in many fields such as PDA systems because of the low power and low cost. It is a general-purpose processor, designed for both efficient digital signal processing and controller operations. But the advent of the wireless communication creates a need for high computational performance for signal processing. And then This paper has been designed a floating-point multiplier compatible to IEEE-754 single precision format for ARMTTDMI performance improvement.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.655-656
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• 2006

A parallel analog Viterbi decoder which decodes PR (1,2,2,1) signal of optical disc has been fabricated into chip. The proposed parallel analog Viterbi decoder implements the functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuits. In this paper, the analog parallel Viterbi decoding technology is applied for the PR signal. The benefit of analog processing is the low power consumption and the less silicon consumption. The test results of the fabricated chip are reported in this paper.

• 전기전자학회논문지
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• 제26권2호
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• pp.299-305
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• 2022

다양한 물리적 신호를 디지털 신호 영역에서 처리하기 위해서 센서의 출력을 디지털로 변환하는 아날로그-디지털 변환기 (ADC)는 시스템 구성에 있어 매우 중요한 구성 블록이다. 센서 신호 처리를 위한 아날로그 회로의 역할을 디지털로 변환하는 추세에 따라 이러한 ADC의 해상도는 높아지는 추세이다. 또한 ADC는 모바일 기기의 배터리 효율 증대를 위해서 저전력 성능이 요구된다. 기존 integrating 시그마-델타 ADC의 경우 고해상도를 가지는 특징이 있지만, 저전압 조건과 미세화 공정으로 인해 적분기의 연산증폭기 이득 오차가 증가해 정확도가 낮아지게 된다. 이득 오차를 최소화하기 위해 버퍼 보상 기법을 적용할 수 있지만 버퍼의 전류가 추가된다는 단점이 있다. 본 논문에서는 이와 같은 단점을 보완하고자 버퍼를 스위칭하며 전류를 최소화시키고, 하이패스 바이어스 회로를 통해 settling time을 향상시켜 기존과 동일한 해상도를 갖는 ADC를 설계하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.217-220
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• 2000

In this paper, A low-power MOS monolithic peak detector is presented. Designed for monolithic and low-power characteristics, this MOS peak detector can be integrated easily on the same chip as a module of large communication systems. The simulation results of this peak detector which was composed with four NMOSs and two capacitors show the power dissipation of 0.972㎽ and the good operations for 2㎓ operating pulse frequency. Therefore, it may be used as a functional block for various signal processing systems.

• 융합신호처리학회논문지
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• 제15권4호
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• pp.141-147
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• 2014

웨이블릿 축소기법은 웨이블릿 변환 계수의 분산 값에 의해 결정되는 경계값을 이용해서 원신호와 잡음신호 간의 MSE(Mean Square Error)가 최소가 되도록 웨이블릿 변환된 계수를 축소하는 방법이다. 이 논문에서는 단조변환 및 웨이블릿 서브밴드의 전력을 이용해서 고주파 및 저주파 웨이블릿 밴드에 적용되는 새로운 경계값들을 제시하고, 이 값들과 ST(soft-threshold) 연산자에 의해 영상신호에 부가된 가우시안 잡음을 제거하였다. 그리고 그 결과를 VisuShrink방법 및 [15]에서의 제시한 기법의 결과와 PSNR로 비교, 평가하고 이 기법의 실용성을 밝혔다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.967-970
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• 1999

A novel linear transconductor for low-voltage low-power signal processing is proposed. The transconductor consists of a pnp differential-pair and a npn differential-pair which are biased by local negative feedback. The simulation results show that the transcondcutor with transconductance of 50 $mutextrm{s}$ has a linearity error of 0.05% and the power dissipation is 2.44 ㎽ over an input linear range from -2V to +2V at supply voltage $\pm$3V.

• IEIE Transactions on Smart Processing and Computing
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• 제3권2호
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• pp.41-51
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• 2014

This paper describes a method to estimate the noise power using the minimum statistics approach, which was originally proposed for audio processing. The proposed minimum statistics-based method separates a noisy image into multiple frequency bands using the three-level discrete wavelet transform. By assuming that the output of the high-pass filter contains both signal detail and noise, the proposed algorithm extracts the region of pure noise from the high frequency band using an appropriate threshold. The region of pure noise, which is free from the signal detail part and the DC component, is well suited for minimum statistics condition, where the noise power can be extracted easily. The proposed algorithm reduces the computational load significantly through the use of a simple processing architecture without iteration with an estimation accuracy greater than 90% for strong noise at 0 to 40dB SNR of the input image. Furthermore, the well restored image can be obtained using the estimated noise power information in parametric image restoration algorithms, such as the classical parametric Wiener or ForWaRD image restoration filters. The experimental results show that the proposed algorithm can estimate the noise power accurately, and is particularly suitable for fast, low-cost image restoration or enhancement applications.

• 전력전자학회논문지
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• 제18권3호
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• pp.225-231
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• 2013

This paper presents an improved signal processing technique in the square-wave-type voltage injection method for IPMSM sensorless drives. Since the sensorless method based on the square-wave voltage injection does not use low-pass filters to get an error signal for estimating rotor position and allows the frequency of the injected voltage signal to be high, the sensorless drive system may achieve an enhanced control bandwidth and reduced acoustic noise. However, this sensorless method still requires low-pass and band-pass filters to extract the fundamental component current and the injected frequency component current from the motor current, respectively. In this paper, these filters are replaced by simple arithmetic operations so that the time delay for estimating the rotor position can be effectively reduced to only one current sampling. Hence, the proposed technique can simplify its whole signal process for the IPMSM sensorless control using the square-wave-type voltage injection. The proposed technique is verified by the experiment on the 800W IPMSM drive system.

• Journal of Information Processing Systems
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• 제18권1호
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• pp.97-114
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• 2022

Interest is increasing in electrocardiogram (ECG) signal analysis for embedded devices, creating the need to develop an algorithm suitable for a low-power, low-memory embedded device. Linear approximation of the ECG signal facilitates the detection of fiducial points by expressing the signal as a small number of vertices. However, dynamic programming, a global optimization method used for linear approximation, has the disadvantage of high complexity using memoization. In this paper, the calculation area and memory usage are improved using a linear approximated template. The proposed algorithm reduces the calculation area required for dynamic programming through local optimization around the vertices of the template. In addition, it minimizes the storage space required by expressing the time information using the error from the vertices of the template, which is more compact than the time difference between vertices. When the length of the signal is L, the number of vertices is N, and the margin tolerance is M, the spatial complexity improves from O(NL) to O(NM). In our experiment, the linear approximation processing time was 12.45 times faster, from 18.18 ms to 1.46 ms on average, for each beat. The quality distribution of the percentage root mean square difference confirms that the proposed algorithm is a stable approximation.