• Journal of Power Electronics
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• v.18 no.2
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• pp.375-382
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• 2018

A novel active controlled primary current cutting-off zero-voltage and zero-current switching (ZVZCS) PWM three-level dc-dc converter (TLC) is proposed in this paper. The proposed converter has some attractive advantages. The OFF voltage on the primary switches is only Vin/2 due to the series connected structure. The leading-leg switches can obtain zero-voltage switching (ZVS), and the lagging-leg switches can achieve zero-current switching (ZCS) in a wide load range. Two MOSFETs, referred to as cutting-off MOSFETs, with an ultra-low on-state resistance are used as active controlled primary current cutting-off components, and the added conduction loss can be neglected. The added MOSFETs are switched ON and OFF with ZCS that is irrelevant to the load current. Thus, the auxiliary switching loss can be significantly minimized. In addition, these MOSFETs are not series connected in the circuit loop of the dc input bus bar and the primary switches, which results in a low parasitic inductance. The operation principle and some relevant analyses are provided, and a 6-kW laboratory prototype is built to verify the proposed converter.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.50 no.7
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• pp.324-332
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• 2001

In this paper, it is suggested that the selection method of parameter of Power System Stabilizer(PSS) with robustness in low frequency oscillation for Static VAR Compensator(SVC) using a Real Variable Elitism Genetic Algorithm(RVEGA). A SVC, one of the Flexible AC Transmission System(FACTS), constructed by a fixed capacitor(FC) and a thyristor controlled reactor(TCR), is designed and implemented to improve the damping of a synchronous generator, as well as controlling the system voltage. The proposed PSS parameters are optimized using RVEGA in order to maintain optimal operation of generator under the various operating conditions. To decrease the computational time, real variable string is adopted. To verify the robustness of the proposed method, we considered the dynamic response of generator speed deviation and generator terminal voltage by applying a power fluctuation and three-phase fault at heavy load, normal load and light load. Thus, we prove the usefulness of proposed method to improve the stability of single machine-infinite bus with SVC system.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.7
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• pp.1150-1156
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• 2008

This paper introduces the PC clustering of the SIMD structure for a distributed processing of on-line contingency to assess a static security of a power system. To execute on-line contingency analysis of a large-scale power system, we need to use high-speed execution device. Therefore, we constructed PC-cluster system using PC clustering method of the SIMD structure and applied to a power system, which relatively shows high quality on the high-speed execution and has a low price. SIMD(single instruction stream, multiple data stream) is a structure that processes are controlled by one signal. The PC cluster system is consisting of 8 PCs. Each PC employs the 2 GHz Pentium 4 CPU and is connected with the others through ethernet switch based fast ethernet. Also, we consider N-1 line contingency that have high potentiality of occurrence realistically. We propose the distributed process algorithm of the SIMD structure for reducing too much execution time on the on-line N-1 line contingency analysis in the large-scale power system. And we have verified a usefulness of the proposed algorithm and the constructed PC cluster system through IEEE 39 and 118 bus system.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.61 no.4
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• pp.186-191
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• 2012

DC Bus Electrolytic capacitors have been widely used in power conversion system because they can achieve high capacitance and voltage ratings with volumetric efficiency and low cost. This type of capacitors have been traditionally used for filtering, voltage smoothing, by-pass and other many applications in power conversion circuits requiring a cost effective and volumetric efficiency components. Unfortunately, electrolytic capacitors are some of the weakest components in power electronic converter. Many papers have proposed different methods or algorithms to determinate the ESR and/or capacitance C for fault diagnosis of the electrolytic capacitor. However, both ESR and C vary with frequency and temperature. Accurate knowledge of both values at the capacitors operating conditions is essential to achieve the best reference data of fault judgement. According to parameter analysis, the capacitance increases with temperature and the ESR decreases. Higher frequencies make the ESR and C to decrease. Analysis results show that the proposed electrolytic capacitor parameter estimation technique can be applied to reference signal of capacitor diagnosis systems successfully.

• Journal of Power Electronics
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• v.18 no.1
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• pp.56-69
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• 2018

In this paper, an improved Space Vector Modulation (SVM) based fault tolerant operation on a nine-level Cascaded H-Bridge (CHB) inverter with an additional backup circuit is proposed. Any type of fault in a power converter may result in a power interruption and productivity loss. Three different faults on H-bridge modules in all three phases based on the SVM approach are investigated with diagrams. Any fault in an inverter phase creates an unbalanced output voltage, which can lead to instability in the system. An additional auxiliary unit is connected in series to the three phase cascaded H-bridge circuit. With the help of this and the redundant switching states in SVM, the CHB inverter produces a balanced output with low harmonic distortion. This ensures high DC bus utilization under numerous fault conditions in three phases, which improves the system reliability. Simulation results are presented on three phase nine-level inverter with the automatic fault detection algorithm in the MATLAB/SIMULINK software tool, and experimental results are presented with DSP on five-level inverter to validate the practicality of the proposed SVM fault tolerance strategy on a CHB inverter with an auxiliary circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.7
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• pp.1610-1618
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• 2014

Wearable computer systems can use the wireless universal serial bus (WUSB) that refers to USB technology that is merged with WiMedia PHY/MAC technical specifications. In this paper, we focus on an integrated system of the wireless USB over the IEEE 802.15.6 wireless body area networks (WBAN) for wireless wearable computer systems supporting U-health services. And a communication structure that performs the hibernation for low power consumption is proposed for WUSB over IEEE 802.15.6 hierarchical protocol. In the proposed hibernation mechanisms, WUSB communications are permitted at each m-periodic inactive periods of WBAN superframes by using the WBAN information of Wakeup Period and Wakeup Phase message fields. In our performance evaluations, performances according to amount of WUSB traffic and Wakeup Periods are analyzed respectively to evaluate the effectiveness of proposed hibernation structure in WUSB over IEEE 802.15.6.

• Plant Journal
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• v.17 no.2
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• pp.48-53
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• 2021

In the case of a 900 MW combined cycle power plant, most of the load on the site is a rotating device and is operated at a low power factor, and the power factor decrease increases the reactive power, which causes the efficiency of the device to be consumed and unnecessary unnecessary power consumption. This study intends to present the results by installing and operating a reactive power compensation device that absorbs and removes reactive power, which is a solution to this problem, on a 6.9 kV on-board bus. As a result of application of this system, first, it was confirmed that the power factor of the rotating machine was improved to 0.22 and the load power in the house was reduced by 1.4%, and the thermal efficiency of the generator was increased by 0.1% and the power generation power by 810 kW. Next, it was confirmed that the cost of construction and operation can be reduced in the future due to economic feasibility, with a decrease of 200 million won/year in electricity loss compared to 1.5 billion won in investment, an increase of 1 billion won/year in sales, and a one-year capital recovery period.

• ETRI Journal
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• v.25 no.5
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• pp.328-336
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• 2003

Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.36-44
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• 2007

This paper presented a hybrid ternary encoding scheme using 3-valued logic. It can adapt to the delay-insensitive(DI) model. We designed an asynchronous wrapper for the hybrid ternary encoding scheme to communicate with various asynchronous encoding schemes. It reduced about 50% of transmission lines and power consumption compared with the conventional 1-of-4 and ternary encoding scheme. The proposed wrappers were designed and simulated using the $0.18-{\mu}m$ standard CMOS technology. As a result, the asynchronous wrapper operated over 2 GHz communicating with a system bus. Moreover, the power dissipation of the system bus adapted the hybrid ternary encoding logic decreases 65%, 43%, and 36% of the dual-rail, 1-of-4, and ternary encoding scheme, respectively. The proposed data encoding scheme and the wrapper circuit can be useful for asynchronous high-speed and low-power asynchronous interface.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.25-31
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• 2009

A low power SRAM using supply voltage charge recycling (SVCR-SRAM) scheme is proposed. It divides into two SRAM cell blocks and supplies two different powers. A supplied power is $V_{DD}$ and $V_{DD}/2$. The other is $V_{DD}/2$ and GND. When N-bit cells are accessed, the charge used in N/2-bit cells with VDD and $V_{DD}/2$ is recycled in the other N/2-bit cells with $V_{DD}/2$ and GND. The SVCR scheme is used in the power consuming parts which bit line, data bus, word line, and SRAM cells to reduce dynamic power. The other parts of SRAM use $V_{DD}$ and GND to achieve high speed. Also, the SVCR-SRAM results in reducing leakage power of SRAM cells due to the body-effect. A 64K-bit SRAM ($8K{\times}8$bits) is implemented in a $0.18{\mu}m$ CMOS process. It saves 57.4% write power and 27.6% read power at $V_{DD}=1.8V$ and f=50MHz.