• Journal of Power Electronics
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• 제18권2호
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• pp.375-382
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• 2018

A novel active controlled primary current cutting-off zero-voltage and zero-current switching (ZVZCS) PWM three-level dc-dc converter (TLC) is proposed in this paper. The proposed converter has some attractive advantages. The OFF voltage on the primary switches is only Vin/2 due to the series connected structure. The leading-leg switches can obtain zero-voltage switching (ZVS), and the lagging-leg switches can achieve zero-current switching (ZCS) in a wide load range. Two MOSFETs, referred to as cutting-off MOSFETs, with an ultra-low on-state resistance are used as active controlled primary current cutting-off components, and the added conduction loss can be neglected. The added MOSFETs are switched ON and OFF with ZCS that is irrelevant to the load current. Thus, the auxiliary switching loss can be significantly minimized. In addition, these MOSFETs are not series connected in the circuit loop of the dc input bus bar and the primary switches, which results in a low parasitic inductance. The operation principle and some relevant analyses are provided, and a 6-kW laboratory prototype is built to verify the proposed converter.

• 대한전기학회논문지:전력기술부문A
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• 제50권7호
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• pp.324-332
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• 2001

In this paper, it is suggested that the selection method of parameter of Power System Stabilizer(PSS) with robustness in low frequency oscillation for Static VAR Compensator(SVC) using a Real Variable Elitism Genetic Algorithm(RVEGA). A SVC, one of the Flexible AC Transmission System(FACTS), constructed by a fixed capacitor(FC) and a thyristor controlled reactor(TCR), is designed and implemented to improve the damping of a synchronous generator, as well as controlling the system voltage. The proposed PSS parameters are optimized using RVEGA in order to maintain optimal operation of generator under the various operating conditions. To decrease the computational time, real variable string is adopted. To verify the robustness of the proposed method, we considered the dynamic response of generator speed deviation and generator terminal voltage by applying a power fluctuation and three-phase fault at heavy load, normal load and light load. Thus, we prove the usefulness of proposed method to improve the stability of single machine-infinite bus with SVC system.

• 전기학회논문지
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• 제57권7호
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• pp.1150-1156
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• 2008

This paper introduces the PC clustering of the SIMD structure for a distributed processing of on-line contingency to assess a static security of a power system. To execute on-line contingency analysis of a large-scale power system, we need to use high-speed execution device. Therefore, we constructed PC-cluster system using PC clustering method of the SIMD structure and applied to a power system, which relatively shows high quality on the high-speed execution and has a low price. SIMD(single instruction stream, multiple data stream) is a structure that processes are controlled by one signal. The PC cluster system is consisting of 8 PCs. Each PC employs the 2 GHz Pentium 4 CPU and is connected with the others through ethernet switch based fast ethernet. Also, we consider N-1 line contingency that have high potentiality of occurrence realistically. We propose the distributed process algorithm of the SIMD structure for reducing too much execution time on the on-line N-1 line contingency analysis in the large-scale power system. And we have verified a usefulness of the proposed algorithm and the constructed PC cluster system through IEEE 39 and 118 bus system.

• 전기학회논문지P
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• 제61권4호
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• pp.186-191
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• 2012

DC Bus Electrolytic capacitors have been widely used in power conversion system because they can achieve high capacitance and voltage ratings with volumetric efficiency and low cost. This type of capacitors have been traditionally used for filtering, voltage smoothing, by-pass and other many applications in power conversion circuits requiring a cost effective and volumetric efficiency components. Unfortunately, electrolytic capacitors are some of the weakest components in power electronic converter. Many papers have proposed different methods or algorithms to determinate the ESR and/or capacitance C for fault diagnosis of the electrolytic capacitor. However, both ESR and C vary with frequency and temperature. Accurate knowledge of both values at the capacitors operating conditions is essential to achieve the best reference data of fault judgement. According to parameter analysis, the capacitance increases with temperature and the ESR decreases. Higher frequencies make the ESR and C to decrease. Analysis results show that the proposed electrolytic capacitor parameter estimation technique can be applied to reference signal of capacitor diagnosis systems successfully.

• Journal of Power Electronics
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• 제18권1호
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• pp.56-69
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• 2018

In this paper, an improved Space Vector Modulation (SVM) based fault tolerant operation on a nine-level Cascaded H-Bridge (CHB) inverter with an additional backup circuit is proposed. Any type of fault in a power converter may result in a power interruption and productivity loss. Three different faults on H-bridge modules in all three phases based on the SVM approach are investigated with diagrams. Any fault in an inverter phase creates an unbalanced output voltage, which can lead to instability in the system. An additional auxiliary unit is connected in series to the three phase cascaded H-bridge circuit. With the help of this and the redundant switching states in SVM, the CHB inverter produces a balanced output with low harmonic distortion. This ensures high DC bus utilization under numerous fault conditions in three phases, which improves the system reliability. Simulation results are presented on three phase nine-level inverter with the automatic fault detection algorithm in the MATLAB/SIMULINK software tool, and experimental results are presented with DSP on five-level inverter to validate the practicality of the proposed SVM fault tolerance strategy on a CHB inverter with an auxiliary circuit.

• 한국정보통신학회논문지
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• 제18권7호
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• pp.1610-1618
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• 2014

웨어러블 컴퓨터 시스템은 WiMedia PHY/MAC 기술과 결합된 USB 기술로 WUSB (wireless universal serial bus) 기술을 사용하여 구성할 수 있다. 본 논문은 U-Health 기능을 지원하는 무선 웨어러블 컴퓨터시스템을 구성하기 위해 WUSB기술과 IEEE 802.15.6 WBAN (wireless body area networks) 기술을 결합한 통신시스템 구조에 초점을 맞추었다. 그리고 IEEE 802.15.6 기반 WUSB 통신 구조에서 저전력 Hibernation 통신 구조를 제안하였다. 제안하는 Hibernation 구조는 WBAN Wakeup Period 및 Wakeup Phase 메시지 필드들을 사용하여, WBAN의 주기적인 Inactive 구간에서 WUSB 통신 구간을 할당한다. 성능 평가에서는 WBAN Wakeup Period에 따른 성능 및 WUSB 통신량에 따른 성능을 비교분석하여, WUSB over IEEE 802.15.6 통신구조에서 제안한 Hibernation 구조의 효율성을 평가하였다.

• 플랜트 저널
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• 제17권2호
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• pp.48-53
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• 2021

900 MW 복합화력발전소의 경우 소내 부하의 대부분은 회전기기이며 저역률로 운전되고 있고 역률 저하는 무효전력을 증가시켜 기기의 효율 저하 및 불필요한 소내 전력을 소비하는 원인이 된다. 본 연구에서는 이러한 문제점을 해결할 수 있는 방안인 무효전력을 흡수 및 제거하는 무효전력보상장치를 6.9 kV 소내 모선에 설치하여 운전함으로써 그에 대한 결과를 제시하고자 한다. 본 시스템의 적용 결과 우선 회전기기의 역률이 0.22로 개선 및 소내 부하전력량 1.4% 감소됨을 확인하였고 발전기 열효율 0.1%, 발전출력810 kW 증가함을 알 수 있었다. 다음으로 투자비 1.5억 원 대비 소내 전력손실비용 2억 원/년 감소 및 매출액 10억 원/년 증가로 경제성 있음으로 분석되었고 향후 건설 및 운영 시 비용절감이 가능함을 확인하였다.

• ETRI Journal
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• 제25권5호
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• pp.328-336
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• 2003

Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.

• 대한전자공학회논문지SD
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• 제44권1호
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• pp.36-44
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• 2007

본 논문은 Delay-Insensitive(DI) 지연 모델을 갖는 비동기식 회로에 3치 전압 레벨을 사용한 하이브리드 터너리 데이터 전송 방식을 제안하고, 이를 이용하여 다양한 비동기 프로토콜과의 데이터 송신 및 수신을 위한 래퍼를 설계하였다. 제안된 하이브리드 터너리 데이터 전송 방식은 기존의 2 선식 전송 방식이나 1-of-4 전송 방식에 비해 데이터 전송선을 50% 줄일 수 있으며, 터너리 전송 방식과 비교하였을 때도 50%의 신호 천이 감소 결과를 보였다. 본 논문에서는 $0.18-{\mu}m$ CMOS 공정을 적용하여 래퍼를 설계하고 검증하였다. 하이브리드 터너리 전송 방식이 적용된 래퍼는 2 GHz 이상의 속도로 동작 하였으며 2 선식, 1-of-4, 그리고 터너리 전송 방식에 비해 각각 65%, 43%, 36%의 소비 전력이 줄어든 결과를 보였다. 제안된 전송 방식과 설계된 래퍼 회로는 비동기식 고속 및 저전력 인터페이스로 사용 가능하다.

• 대한전자공학회논문지SD
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• 제46권5호
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• pp.25-31
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• 2009

본 논문에서는 공급전압의 전하를 재활용하여 전력소모를 줄인 저전력 SRAM(Low power SRAM using supply voltage charge recycling: SVCR-SRAM)을 제안하였다. 제안한 SVCR-SRAM은 SRAM 셀 블록을 두 개의 셀 블록으로 나누어 두 종류의 공급전압을 공급한다. 이중 하나는 $V_{DD}$와 $V_{DD}/2$이고, 다른 하나는 $V_{DD}/2$와 GND이다. N비트 셀들이 연결되었을 때 $V_{DD}$와 $V_{DD}/2$의 전원으로 동작하는 N/2비트의 셀들에서 사용된 전하는 나머지 $V_{DD}/2$와 GND의 전원으로 동작하는 N/2비트의 셀들에서 재활용된다. SVCR 기법은 전력소모가 많은 비트라인, 데이터 버스, SRAM 셀에서 사용되어 전력소모를 줄여준다. 다른 부분들에서는 동작속도를 높이기 위해 $V_{DD}$와 GND의 공급전압을 사용하였다. 또한, SVCR-SRAM에서는 Body-effect로 인한 SRAM 셀들의 누설전류가 크게 감소하는 효과가 있다. 검증을 위하여, 64K비트($8K{\times}8$비트)SRAM chip을 $V_{DD}=1.8V,\;0.18{\mu}m$ CMOS 공정으로 구현하였다. 제작된 SVCR-SRAM에서는 쓰기전력의 57.4%와 읽기전력의 27.6%가 줄었다.