• Electronics and Telecommunications Trends
• /
• v.35 no.2
• /
• pp.69-78
• /
• 2020

Small portable devices such as mobile phones and laptops currently display a trend of high power consumption owing to their characteristics of high speed and multifunctionality. Low-power SoC design is one of the important factors that must be considered to increase portable time at limited battery capacities. Popular low power SoC design techniques include clock gating, multi-threshold voltage, power gating, and multi-voltage design. With a decreasing semiconductor process technology size, leakage power can surpass dynamic power in total power consumption; therefore, appropriate low-power SoC design techniques must be combined to reduce power consumption to meet the power specifications. This study examines several low-power SoC design trends that reduce semiconductor SoC dynamic and static power using EDA tools. Low-power SoC design technology can be a competitive advantage, especially in the IoT and AI edge environments, where power usage is typically limited.

• The Magazine of the IEIE
• /
• v.25 no.5
• /
• pp.31-41
• /
• 1998

With the advent of portable electronic systems, power consumption has recently become a major issue in circuit and system design. Furthermore, the sophisticated fabrication technology makes it possible to embed more functions and features in a VLSI chip, consequently calling for both higher performance and lower power to deal with the ever growing complexity of system algorithms than in the past. VLSI designers should cope with two conflicting constraints, high performance and low power, offering an optimum trade off of these constraints to meet requirements of system. Historically, VLSI designers have focused on performance improvement, and power dissipation was not a design criteria but an afterthought. This design paradigm should be changed, as power is emerging as the most critical design constraint. In VLSI design, low power design can be accomplished through many ways, for instance, process, circuit/logic design, architectural design, and etc.. In this paper, a few low power design examples, which have been used in 8 bit micro-controller core, and can be used also in 4/16/32 bit micro-controller cores, are presented in the areas of circuit, logic and architectural design. We first propose a low power guidelines for micro-controller design in SAMSUNG, and more detailed design examples are followed applying 4 specific design guidelines. The 1st example shows the power reduction through reduction of number of state clocks per instruction. The 2nd example realized the power reduction by applying RISC(Reduced Instruction Set Computer) concept. The 3rd example is to optimize the algorithm for ALU(Arithmetic Logic Unit) to lower the power consumption, Lastly, circuit cells designed for low power are described.

• Magazine of the Korean Society of Agricultural Engineers
• /
• v.37 no.E
• /
• pp.1-9
• /
• 1995

It is shown that two step power transformation is more efficient for the normalization of frequency distribution with the coefficient of skewness of zero in comparison with others including SMEMAX and power transformations. It is confirmed that the design low flows calculated using power and two step power transformations used in this study are generally nearer to the observed data as compared with those of SMEMAX transformation at all return periods in the applied watersheds of the Kum, Naktong and Yongsan rivers in Korea.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.11 no.5
• /
• pp.475-480
• /
• 2018

In OFDM-based systems, FFT is a critical component since it occupies large area and consumes more power. In this paper, we present a low hardware-cost and low power 512-point pipelined FFT design method for OFDM applications. To reduce the number of twiddle factors and to choose simple design architecture, the radix-$2^4-2^3$ algorithm are exploited. For twiddle factor multiplication, we propose a new canonical signed digit (CSD) complex multiplier design method to minimize the hardware-cost. In hardware implementation with Intel FPGA, the proposed FFT design achieves more than about 28% reduction in gate count and 18% reduction in power consumption compared to the previous approaches.

• Magazine of the Korean Society of Agricultural Engineers
• /
• v.34 no.4
• /
• pp.39-47
• /
• 1992

Derivation of reasonable design low flows was attempted by comparative analysis of design low flows was derived by Power and SMEMAX transformations for the normalizations of skewed distribution and by Type m extremal distribution presented in the first report of this study with annual low flows in the five watersheds of main river basins in Korea. The results were anslyzed and summarized as follows. 1.Basic statistics of annual low flows for the selected watersheds were calculated by using Power and SMEMAX transformations. 2.Power thansformation has found to be the best for the normalization of skewed distribution among others including log, square root and SMEMAX transformations. 3.Design low flows for the selected watersheds were derived by the Power and SMEMAX transformations. 4.Judging by the relative suitabilities of the Type III extremal distribution, Power and SMEMAX transformation, it was found that design low flows of all methods are closer to the observed data within 10 years of the return period and those of Power transformation can be acknowledzed as a reasonable one among others from the viewpoint of the median between values of Type m extremal distribution and SMEMAX transformation in addition to closing the observed than others over 10 years of the return period.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.8 no.4
• /
• pp.195-204
• /
• 2013

The embedded software has been developed in the forms of various versions that provides similar service based on product family. For increase usefulness of product family, software must has well-structured and reusable properties. Software architecture is important to improve adaptability in model-based development of embedded software mounted onto product family. In this paper, we proposed a technique of ADD(Attribute-Driven Design)-based software architecture design for low power software development. This technique provides a chance to consider the power consumption issue in design phase of software, and makes possible to develop low power embedded software.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.26 no.3
• /
• pp.190-193
• /
• 2013

Power MOSFET and Power IGBT is develop in power savings, high efficiency, small size, high reliability, fast switching, low noise. Power MOSFET can be used high-speed switching transistors devices. Power MOSFET is devices the voltage-driven approach switching devices are design to handle on large power, power supplies, converters. In this paper, design the 80V MOSFET Planar Gate type, and design the Trench Gate type for realization of low on-resistance. For both structures, by comparing and analyzing the results of the simulation and characterization.

• Proceedings of the KIPE Conference
• /
• 2004.07b
• /
• pp.677-681
• /
• 2004

This paper presents the design and implementation of a low-profile power supply developed for AC-PDP application systems. In the proposed power supply, planar magnetics and SMD devices are integrated into advanced power conversion techniques to implement a low-profile power supply applicable to most AC-PDP application systems. Engineering details on the design and fabrication of planar magnetic components are presented. The performance of the prototype power supply is also demonstrated to validate the application potentials of the proposed power supply.

• Proceedings of the KIEE Conference
• /
• 2003.04a
• /
• pp.163-165
• /
• 2003

Over the past several years, the application extent of the real-time systems is being expanded with the progress of civilization. An effort to minimize power consumption at the system is being accomplished in several fields from the design of an analog/digital circuit up to the device level Things of this effort have included the power optimum-technique to minimize power consumption at the digital logic circuit and the dynamic managed skill by means o( the decision of the operating system. In this paper, we designed of low power system by using Power-optimized method. As an effective low-power design, we designed the low power system which it has a monitoring system within the main board and a personal computer.

• Journal of IKEEE
• /
• v.12 no.1
• /
• pp.27-33
• /
• 2008

The demand of wireless communication is increased rapidly due to the development of wireless communication systems, and many people have the great interest about the "RF system". The trend of the RF audio system is to design the system with less power consumption. In this paper, we explain the Software Algorithm Design of RF systems that is suitable for low power consumption.