• Title/Summary/Keyword: Low-Power Device

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Spectrum Reuse Schemes with Power Control for Device-to-Device Communication in LTE-Advanced Cellular Network

  • Chhorn, Sok;Yoon, Seok-Ho;Seo, Si-O;Kim, Seung-Yeon;Cho, Choong-Ho
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.9 no.12
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    • pp.4819-4834
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    • 2015
  • The spectral efficiency of cellular networks can be improved when proximate users engage in device-to-device (D2D) communications to communicate directly without going through a base station. However, D2D communications that are not properly designed may generate interference with existing cellular networks. In this paper, we study resource allocation and power control to minimize the probability of an outage and maximize the overall network throughput. We investigate three power control-based schemes: the Partial Co-channel based Overlap Resource Power Control (PC.OVER), Fractional Frequency Reuse based Overlap Resource Power Control (FFR.OVER) and Fractional Frequency Reuse based Adaptive Power Control (FFR.APC) and also compare their performance. In PC.OVER, a certain portion of the total bandwidth is dedicated to the D2D. The FFR.OVER and FFR.APC schemes combine the FFR techniques and the power control mechanism. In FFR, the entire frequency band is partitioned into two parts, including a central and edge sub-bands. Macrocell users (mUEs) transmit using uniform power in the inner and outer regions of the cell, and in all three schemes, the D2D receivers (D2DRs) transmit with low power when more than one D2DRs share a resource block (RB) with the macrocells. For PC.OVER and FFR.OVER, the power of the D2DRs is reduced to its minimum, and for the FFR.APC scheme, the transmission power of the D2DRs is iteratively adjusted to satisfy the signal to interference ratio (SIR) threshold. The three schemes exhibit a significant improvement in the overall system capacity as well as in the probability of a user outage when compared to a conventional scheme.

A Design of High-Speed Level-Shifter using Reduced Swing and Low-Vt High-Voltage Devices (Reduced Swing 방식과 Low-Vt 고전압 소자를 이용한 고속 레벨시프터 설계)

  • Seo, Hae-Jun;Kim, Young-Woon;Ryu, Gi-Ju;Ahn, Jong-Bok;Cho, Tae-Won
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.525-526
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    • 2008
  • This paper proposes a new high-speed level shifter using a special high voltage device with low threshold voltage. Also, novel low voltage swing method is proposed. The high voltage device is a standard LDMOS(Laterally Diffused MOS) device in a $0.18{\mu}m$ CMOS process without adding extra mask or process step to realize it. A level shifter uses 5V LDMOSs as voltage clamps to protect 1.8V NMOS switches from high voltage stress the gate oxide. Also, level-up transition from 1.8V to 5V takes only 1.5ns in time. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.

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Power Factor Improvement of Single-Phase Three-level Boost Converter (단상 Three-level boost converter의 역률개선)

  • 서영조
    • Proceedings of the KIPE Conference
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    • 2000.07a
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    • pp.384-387
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    • 2000
  • In this paper Power factor correction circuit of single-phase three-level boost converter is proposed. The advantage of the proposed control scheme for three-level boost converter are low blocking voltage of each power device low THD(Total Harmonic Distortion) and high power factor. The control scheme is based on the current comparator capacitor compensator and region detector, In simulations the proposed system is validated.

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Comparative Performance Analysis of High Speed Low Power Area Efficient FIR Adaptive Filter

  • Jaiswal, Manish
    • IEIE Transactions on Smart Processing and Computing
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    • v.3 no.5
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    • pp.267-270
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    • 2014
  • This paper presents the comparative performance of an adaptive FIR filter for a Delayed LMS algorithm. The delayed error signal was used to obtain a Delayed LMS algorithm to allow efficient pipelining for achieving a small critical path and area efficient implementation. This paper presents hardware efficient results (device utilization parameters) and power consumed. The FPGA families (Artix-7, Virtex-7, and Kintex-7) for a low voltage perspective are shown. The synthesis results showed that the artix-7 CMOS family achieves the lowest power consumption of 1.118 mW with 83.18 % device utilization. Different Precision strategies, such as the speed optimization and power optimization, were imposed to achieve these results. The algorithm was implemented using MATLAB (2013b) and synthesized on the Leonardo spectrum.

Performance Evaluation of Distributed MAC Protocol Algorithm for Efficient Multimedia Transmission (효율적인 멀티미디어 전송을 위한 분산방식 MAC 프로토콜 성능분석)

  • Kim, Jin Woo;Lee, Seong Ro
    • Journal of Korea Multimedia Society
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    • v.17 no.5
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    • pp.573-581
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    • 2014
  • The salient features of UWB(Ultra WideBand) networks such as high-rate communications, low interference with other radio systems, and low power consumption bring many benefits to users, thus enabling several new applications such as wireless universal serial bus (WUSB) for connecting personal computers (PCs) to their peripherals and the consumer-electronics (CE) in people's living rooms. Because the size of multimedia data frame, WiMedia device must transmit the fragment of MSDU. However, when the fragment of MSDU is lost, WiMedia device maintains active mode for the time to complete the transmission MSDU, and there is a problem that unnecessary power consumption occurs. Therefore we propose new power management scheme to reduce unnecessary power consumption of WiMedia devices in the case that the fragment is lost.

A Study on the 0.5$\mu\textrm{m}$ Dual Gate High Voltage Process for Multi Operation Applications (Multi Operation을 위한 0.5$\mu\textrm{m}$Dual Gate 고전압 공정에 관한 연구)

  • 송한정;김진수;곽계달
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.11a
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    • pp.463-466
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    • 2000
  • According to the development of the semiconductor micro device technology, IC chip trends the high integrated, low power tendency. Nowadays, it can be showed the tendency of single chip in system level. But in the system level, IC operates by multi power supply voltages. So, semiconductor process is necessary for these multi power operation. Therefore, in this paper, dual gate high voltage device that operate by multi power supply of 5V and 20V fabricated in the 0.5${\mu}{\textrm}{m}$ CMOS process technology and its electrical characteristics were analyzed. The result showed that the characteristics of the 5V device almost met with the SPICE simulation, the SPICE parameters are the same as the single 5V device process. And the characteristics of 20V device showed that gate length 3um device was available without degradation. Its current was 520uA/um, 350uA/um for NMOS, PMOS and the breakdown voltages were 25V, 28V.

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Study on the Energy Harvesting System Using Piezoelectric Direct Effect of Piezo Film (압전 필름의 압전정 효과를 이용한 에너지 저장 시스템에 관한 연구)

  • Choi, Bum-Kyoo;Lee, Woo-Hun
    • Journal of the Korean Society for Precision Engineering
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    • v.25 no.9
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    • pp.78-85
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    • 2008
  • Piezoelectric materials have been investigated as vibration energy converters to power wireless devices or MEMS devices due to the recent low power requirements of such devices and the advancement in miniaturization technology. Piezoelectric power generation can be an alternative to the traditional power source-battery because of the presence of facile vibration sources in our environment and the potential elimination of the maintenance required for large volume batteries. This paper represents the new power source which supplies energy device node. This system, called "energy harvesting system", with piezo materials scavenges extra energy such as vibration and acceleration from the environment. Then it converts the mechanical energy scavenged to electrical energy for powering device This paper explains the properties of piezo material through theoretical analysis and experiments The developed system provides a solution to overcome the critical problem of making up wireless device networks.

Highly AC Voltage Fluctuation-Resistant LED Driver with Sinusoid-Like Reference

  • Ning, Ning;Tong, Zhenxiao;Yu, Dejun;Wu, Shuangyi;Chen, Wenbin;Feng, Chunyi
    • Journal of Power Electronics
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    • v.14 no.2
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    • pp.257-264
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    • 2014
  • A novel converter-free AC LED driver that is highly resistant to the fluctuation of AC voltage is proposed in this study. By removing large passive components, such as the bulky capacitor and the large-value inductor, the integration of the driver circuit is enhanced while the driving current remains stable. The proposed circuit provides LED lamps with a driving current that can follow the sinusoid waveform to obtain a very high power factor (PF) and low total harmonic distortion (THD). The LED input current produced by this driving current is insensitive to fluctuations in the AC voltage. Users will thus not feel that LED lamps are flashing during the fluctuation. Experiment results indicate that the proposed system can obtain PF of 0.999 and THD as low as 3.3% for a five-string 6 W LED load under 220 V at 50 Hz.

Design and Implementation of Low-power CSD Considering Beacon Period and Channel Scan Time (비컨 주기와 채널 탐색기간을 고려한 저전력 CSD의 설계 및 구현)

  • Kim, Taek-Hyun;Park, Se-Young;Choi, Hoon;Baek, Yun-Ju
    • Journal of KIISE:Computing Practices and Letters
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    • v.16 no.1
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    • pp.50-54
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    • 2010
  • A Container Security Device (CSD) which is different existing RFID Tag strengthens the physical security as mounted inside the container and the information security as encrypts doubly a data. CSD must use the resources efficiently in order to operate with the battery. Therefore, it needs low-power mechanism which repeats the sleep period and channel scan period. However, by adjusting these periods, the trade-off occurs between energy efficiency and network connectivity. In this paper, we implement low-power CSD and resolve this problem by adjusting beacon period and channel scan time. As a result, We guarantee the network connectivity 95% or more and maximum life up to 16 days using common AA batteries.

Design of the low-power system using the limited source (제한된 전원을 사용하는 저전력 시스템 설계)

  • Kim, Do-Hun;Lee, Kyo-Sung;Kim, Yong-Sang;Park, Jong-Chul;Kim, Yang-Mo
    • Proceedings of the KIEE Conference
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    • 2003.04a
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    • pp.163-165
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    • 2003
  • Over the past several years, the application extent of the real-time systems is being expanded with the progress of civilization. An effort to minimize power consumption at the system is being accomplished in several fields from the design of an analog/digital circuit up to the device level Things of this effort have included the power optimum-technique to minimize power consumption at the digital logic circuit and the dynamic managed skill by means o( the decision of the operating system. In this paper, we designed of low power system by using Power-optimized method. As an effective low-power design, we designed the low power system which it has a monitoring system within the main board and a personal computer.

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