• 정보처리학회논문지A
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• 제17A권3호
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• pp.121-126
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• 2010

본 논문에서는 저 전압 스윙 기술을 적용하여 저 전력 회로를 구현하고, 슬립 트랜지스터 (sleep-transistor)를 이용하여 누설전류를 최소화하는 새로운 저 전력 MOS 전류모드 논리회로 (MOS current-mode logic circuit)를 제안하였다. 제안한 회로는 저 전압 스윙 기술을 적용하여 저 전력 특성을 갖도록 설계하였고 고 문턱전압 PMOS 트랜지스터 (high-threshold voltage PMOS transistor)를 슬립 트랜지스터로 사용하여 누설전류를 최소화하였다. 제안한 회로는 $16\;{\times}\;16$ 비트 병렬 곱셈기에 적용하여 타당성을 입증하였다. 이 회로는 슬립모드에서 기존 MOS 전류 모드 논리회로 구조에 비해 대기전력소모가 1/104로 감소하였으며, 정상 동작모드에서 11.7 %의 전력소모 감소효과가 있었으며 전력소모와 지연시간의 곱에서 15.1 %의 성능향상이 있었다. 이 회로는 삼성 $0.18\;{\mu}m$ CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.212-215
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• 2002

In this paper, we present an intermediate representation CDFG(Control Data Flow Graph) and an efficient scheduling technique for low power circuit design. The proposed CDFG represents control flow, data dependency and such constraints as resource constraints and timing constraints. In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the inclusion and overlap relation efficiently. Also, iterative rescheduling process are performed in a minimum bound estimation, starting with the as soon as possible as scheduling result, so as to reduce the power consumption in low power design. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.

• 전자공학회논문지C
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• 제34C권12호
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• pp.20-27
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• 1997

In this paper, a multiplying digital-to-analog converter (MDAC) circuit for low-power high-resolution CMOS algorithmic A/D converters (ADC's) is proposed. The proposed MDAC is designed to operte properly at a supply at a supply voltge between 3 V and 5 V and employs an analog0domain power reduction technique based on a bias switching circuit so that the total power consumption can be optimized. As metal-to-metal capacitors are implemented as frequency compensation capacitors, opamps' performance can be varied by imperfect process control. The MDAC minimizes the effects by the circuit performance variations with on-chip tuning circuits. The proposed low-power MDAC is implementd as a sub-block of a 10-bit 200kHz algorithmic ADC using a 0.6 um single-poly double-metal n-well CMOS technology. With the power-reduction technique enabled, the power consumption of the experimental ADC is reduced from 11mW to 7mW at a 3.3V supply voltage and the power reduction ratio of 36% is achieved.

• 한국전자통신학회논문지
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• 제10권5호
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• pp.587-592
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• 2015

LED의 사용이 증가됨에 따라, LED 디스플레이의 저전력 설계에 대한 요구가 증가하고 있다. 본 논문에서는 디지털 신호로 제어하는 정전류원 회로에 단열회로 동작을 유도하는 전원소스 공급을 통하여, 저전력화가 가능한 LED 컨트롤러부를 설계하였다. 설계한 회로는 0.35um CMOS Process로 구현하였으며 회로의 선형 동작을 확인하였다. 시뮬레이션 결과 기존의 LED 컨트롤러부에 대비하여 약 82% 소비전력 절감효과를 확인하였다. 본 연구는 LED 디스플레이 동작의 발열 대책 및 저전력화에 유용할 것으로 기대된다.

• 한국통신학회논문지
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• 제25권8B호
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• pp.1477-1486
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• 2000

본 논문에서는 조합 논리 회로의 면적과 전력 소모를 낮추기 위한 효율적인 커널 기반의 분할 알고리듬을 제안 한다. 제안한 알고리듬은 커널을 이용하여 회로를 분할함으로써 회로의 전력 소모를 줄이고 분할된 회로들의 중복 되는 게이트를 최소화시켜 면적 overhead를 감소시킨다. MCNC 표준 테스트 회로에 대한 실험을 통하여 제안된 알고리듬이 면적과 전력소모면에 있어서 기존의 precomputation 회로 구조에 바탕을 둔 알고리듬에 비해 전력 소모는 평균 43.6% 면적은 평균30.7% 향상된 결과를 보인다.

• Journal of Electrical Engineering and Technology
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• 제3권1호
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• pp.130-134
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• 2008

The increasing size of very large scale integration (VLSI) circuits, high transistor density, and popularity of low-power circuit and system design are making the minimization of power dissipation an important issue in VLSI design. Test Power dissipation is exceedingly high in scan based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain or cell modification lead to reduced dissipations of power. The ETC algorithm of previous work has weak points. Taking all of this into account, we therefore propose a new algorithm. Its name is RE_ETC. The proposed modifications in the scan chain consist of Exclusive-OR gate insertion and scan cell reordering, leading to significant power reductions with absolutely no area or performance penalty whatsoever. Experimental results confirm the considerable reductions in scan chain transitions. We show that modified scan cell has the improvement of test efficiency and power dissipations.

• Journal of Power Electronics
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• 제16권4호
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• pp.1256-1267
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• 2016

Distributed stray inductance exerts a significant influence on the turn-off voltages of power switching devices. Therefore, the design of low stray inductance bus bars has become an important part of the design of high-power converters. In this study, we first analyze the operational principle and switching transient of a T-type converter. Then, we obtain the commutation circuit, categorize the stray inductance of the circuit, and study the influence of the different types of stray inductance on the turn-off voltages of switching devices. According to the current distribution of the commutation circuit, as well as the conditions for realizing laminated bus bars, we laminate the bus bar of the converter by integrating the practical structure of a capacitor bank and a power module. As a result, the stray inductance of the bus bar is reduced, and the stray inductance in the commutation circuit of the converter is reduced to more than half. Finally, a 10 kVA experimental prototype of a T-type converter is built to verify the effectiveness of the designed laminated bus bar in restraining the turn-off voltage spike of the switching devices in the converter.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.221-224
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• 2004

This paper proposed an ultra low-power CMOS exponential voltage-mode circuit using the Pseudo-exponential function for realizing the exponential characteristics. The proposed circuit provides high dB-linear output voltage range at low-voltage applications. In a $0.25\;\mu m$ CMOS process, the simulations show more than 35 dB output voltage range and 26 dB with the linearity error less than $\pm0.5\;dB.$ The average current consumption is less than 80 uA. The proposed circuit can be used for the design of an extremely low-power variable gain amplifier (VGA) and automatic gain control (AGC).

• Journal of Power Electronics
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• 제15권4호
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• pp.1018-1025
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• 2015

This paper proposes a methodological scheme for the photovoltaic (PV) simulator design. With the advantages of a digital controller system, linear interpolation is proposed for precise fitting with higher computational efficiency. A novel control strategy that directly tackles two different duty cycles is proposed and implemented to achieve a full-range operation including short circuit (SC) and open circuit (OC) conditions. Systematic design procedures for both hardware and algorithm are explained, and a prototype is built. Experimental results confirm an accurate steady state performance under different load conditions, including SC and OC. This low power apparatus can be adopted for PV education and research with a limited budget.

• 정보처리학회논문지A
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• 제14A권3호
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• pp.147-150
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• 2007

본 논문에서는 작은 점유면적과 저 전력 소모 특성을 갖도록 CPL(Complementary Pass-Transistor Logic) 논리구조의 전가산기에 저 전압 스윙 기술을 적용하여 16$\times$16 비트 병렬 곱셈기를 설계하였다. 회로구성상 CPL 논리구조는 CMOS 논리구조에 비해 NMOS 트랜지스터만을 사용하기 때문에 작은 면적을 소비한다. 저 전압 스윙 기술은 회로에 공급되는 전압보다 낮은 전압 레벨에서 출력 동작을 하여 전력 소모를 감소시키는 기술이다. 본 논문에서는 전가산기의 출력 단에 사용되는 인버터에 저 전압 스윙 기술을 적용하여 저 전력 소모 특성을 갖는 16$\times$16 비트 병렬 곱셈기를 설계하였다 설계한 회로는 17.3%의 전력 소모 감소와 16.5%의 전력소모와 지연시간의 곱(Power Delay) 감소가 이루어졌다.