• Journal of Information Processing Systems
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• v.15 no.6
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• pp.1406-1421
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• 2019

The Internet-of-Things (IoT) has been deployed in almost every facet of our day to day activities. This is made possible because sensing and data collection devices have been given computing and communication capabilities. The devices implement System-on-Chips (SoCs) that incorporate a lot of functionalities, yet they are severely constrained in terms of memory capacitance, hardware area, and power consumption. With the increase in the functionalities of sensing devices, there is a need for low-cost synthesizable processors to handle control, interfacing, and error processing. The first step in selecting a synthesizable processor core for low-cost devices is to examine the hardware resource utilization to make sure that it fulfills the requirements of the device. This paper gives an analysis of the hardware resource usage of ten synthesizable processors that implement the Reduced Instruction Set Computer Five (RISC-V) Instruction Set Architecture (ISA). All the ten processors are synthesized using Vivado v2018.02. The maximum frequency, area, and power reports are extracted and a comparison is made to determine which processor is ideal for low-cost hardware devices.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.1
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• pp.69-77
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• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.

• Journal of the Korea Society of Computer and Information
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• v.18 no.6
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• pp.1-8
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• 2013

In this paper, we design and implement a firmware for low-cost small PCR devices. To minimize machine code size, the proposed firmware controls real-time tasks simultaneously only with support of the hardware interrupt, but without support of the operating system program. The proposed firmware has the host-local structure in which the firmware receives operation commands from PC and sends operation results to PC through usb communication. We implement a low-cost small PCR device with the proposed firmware loaded on microchip PIC18F4550 chip, and verify that the implemented PCR device significantly reduces cost and volume size of existing commercial PCR devices with a similar performance.

• Electronics and Telecommunications Trends
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• v.37 no.5
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• pp.44-53
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• 2022

The Internet of Things (IoT) is growing exponentially, with the number of IoT devices multiplying annually. Accordingly, the paradigm is changing from cloud computing to edge computing and even tiny edge computing because of the low latency and cost reduction. Machine learning is also shifting its role from the cloud to edge or tiny edge according to the paradigm shift. However, the fragmented and resource-constrained features of IoT devices have limited the development of artificial intelligence applications. Edge MLaaS (Machine Learning as-a-Service) has been studied to easily and quickly adopt machine learning to products and overcome the device limitations. This paper briefly summarizes what Edge MLaaS is and what element of research it requires.

• Journal of IKEEE
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• v.19 no.1
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• pp.45-51
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• 2015

Recently, as WPAN (Wireless Personal Area Network) becomes the necessary feature in IoT (Internet of Things) devices, the importance of data security also hugely increases. In this paper, we present the low-complexity 128-bit AES-$CCM^*$ hardware IP for IEEE 802.15.4 standard. For low-cost and low-power implementation which is essentially required in IoT devices, we propose two optimization methods. First, the folded AES(Advanced Encryption Standard) processing core with 8-bit datapath is presented where composite field arithmetic is adopted for reduced hardware complexity. In addition, to support $CCM^*$ mode defined in IEEE 802.15.4, we propose the mode-toggling architecture which requires less hardware resources and processing time. With the proposed methods, the gate count of the proposed AES-$CCM^*$ IP can be lowered up to 57% compared to the conventional architecture.

• International Journal of Internet, Broadcasting and Communication
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• v.13 no.1
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• pp.20-25
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• 2021

In the background of the rapid development of the IoT, smart home work is becoming more and more important to each science and technology company. Smart home provides a safe, comfortable, high-quality, high-performance smart home living space compared to general homes, and at the same time It is responding to the low-carbon, eco-friendly global trend. Growth drivers driving the smart home market are increasing the number of Internet users, increasing disposable income in developing countries, increasing the importance of remote home monitoring, and increasing the need for energy saving and low carbon. In 2013-2014, Xiaomi launched a series of smart routers and smart home hardware devices. In 2015, it announced the latest product of the Xiaomi Ecological Chain, the "Smart Home Package," and in 2016 launched the MIJIA brand to invest in various smart product companies. In 2017, Xiaomi announced a plan to build an open smart hardware MIOT platform. We investigated the management strategy of Xiaomi home smart service based on IOT. The management strategy was divided into cost lead strategy, differentiation strategy of Xiaomi home service, and AIOT strategy of Xiaomi smart home.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.1011-1012
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• 2006

In this paper, implementation process of standard platform for T-DMB Receiver in low-cost and small-size are following: First, implement SoC for 32 bit RISC CPU and 16 bit DSP, Hardware H.264 CODEC, Post Processor or Video Display, Audio Processor, I/O Device. Second, implement Real Time OS for flexible application. Third, propose simple architecture for interface with peripheral devices using one-chip processor.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.5
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• pp.253-259
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• 2018

Recently, small satellite industries are rapidly changing. Demand for high performance small satellites is increasing with the expansion of Earth Observation Satellite market. A next-generation small satellites require a higher resolution image storage capacity than before. However, there is a problem that the HW configuration of the existing small satellite image storage device could not meet these requirements. The conventional data storing system uses SDRAM to store image data taken from satellites. When SDRAM is used in small satellite platform of a next generation, there is a problem that the cost of physical space is eight times higher and satellite price is two times higher than NAND Flash. Using the same satellite hardware configuration for next-generation satellites will increase the satellite volume to meet hardware requirements. Additional cost is required for structural design, environmental testing, and satellite launch due to increasing volume. Therefore, in order to construct a low-cost, high-efficiency system. This paper shows a next-generation solid state recorder unit (SSRU) using MRAM and NAND Flash instead of SDRAM. As a result of this research, next generation small satellite retain a storage size and weight and improves the data storage space by 15 times and the storage speed by 4.5 times compare to conventional design. Also reduced energy consumption by 96% compared to SDRAM based storage devices.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.372-376
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• 2001

Due to several advantages of Pulse Width Modulation(PWM) Converter, such as unity power factor operation, elimination of low-order harmonics and regeneration of motor braking energy to source, the application range of PWM Converter has been rapidly extended in industrial application. Nowadays, vector control algorithm and space vector PWM(SVPWM) method are applied to improve the performances of PWM Converter, but vector control algorithm and SVPWM require to use Microprocessor and other digital devices in hardware, causing costly and somewhat large dimension system. In every practical application of energy conversion equipments, the design and implementation should be carried out considering cost and performance. High performance and low cost is the best choice for energy conversion equipments. So, this paper presents the practical design method and implementation results of 3-phase PWM Converter with analog hysteresis current controller, and verifies the performances of unit power factor operation and energy regeneration operation via experimental results.

• Journal of Industrial Technology
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• v.21 no.B
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• pp.117-123
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• 2001

In a modern control field, a control engineer who has theoretical backgrounds with some practical knowledge is demanded. That is to say, an engineer who can understand and operate the various parts such as modeling, simulation, system analysis, signal processing, statistics, and hardware is required. In order to prove the theoretical backgrounds and operate various hardwares, a lot of experimental devices for students are designed in universities. Since the conventional experimental devices are manufactured abroad and the prices of the devices are too high, it is difficult to have. If a low cost experimental device can be developed, it will be very useful for a control engineering education. In Ibis paper, an experimental rig which has two control inputs and three sensor outputs to control the end point of a flexible beam is designed and manufactured. This rig can be used for a control field education.