• Journal of Information Processing Systems
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• 제15권6호
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• pp.1406-1421
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• 2019

The Internet-of-Things (IoT) has been deployed in almost every facet of our day to day activities. This is made possible because sensing and data collection devices have been given computing and communication capabilities. The devices implement System-on-Chips (SoCs) that incorporate a lot of functionalities, yet they are severely constrained in terms of memory capacitance, hardware area, and power consumption. With the increase in the functionalities of sensing devices, there is a need for low-cost synthesizable processors to handle control, interfacing, and error processing. The first step in selecting a synthesizable processor core for low-cost devices is to examine the hardware resource utilization to make sure that it fulfills the requirements of the device. This paper gives an analysis of the hardware resource usage of ten synthesizable processors that implement the Reduced Instruction Set Computer Five (RISC-V) Instruction Set Architecture (ISA). All the ten processors are synthesized using Vivado v2018.02. The maximum frequency, area, and power reports are extracted and a comparison is made to determine which processor is ideal for low-cost hardware devices.

• 한국산업융합학회 논문집
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• 제24권1호
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• pp.69-77
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• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.

• 한국컴퓨터정보학회논문지
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• 제18권6호
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• pp.1-8
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• 2013

본 논문에서는 저가의 소형 PCR 장치에 적합한 펌웨어를 설계하고 구현하였다. 제안된 펌웨어는 실행코드 크기를 최소화하기 위해서 운영체제의 도움을 받지 않고 하드웨어 인터럽트만을 이용하여 실시간 작업들을 동시에 제어한다. 또한 제안된 펌웨어는 usb 통신을 이용하여 PC로부터 동작 과정을 입력받아 마이크로콘트롤러에 연결된 부속장비들을 구동하고, 구동결과를PC로 전달하여 사용자에게 출력하는 주컴퓨터-국소장치 구조에 적합하도록 설계되었다. 제안된 펌웨어를 microchip사의 PIC18F4550 칩에 실제로 탑재하여 저가의 소형 PCR 장치를 제작하였고, 제작한 PCR 장치가 기존 상용 PCR 장치는 제작 비용과 부피를 대폭 줄이면서도 유사한 DNA 증폭 결과를 보임을 확인하였다.

• 전자통신동향분석
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• 제37권5호
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• pp.44-53
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• 2022

The Internet of Things (IoT) is growing exponentially, with the number of IoT devices multiplying annually. Accordingly, the paradigm is changing from cloud computing to edge computing and even tiny edge computing because of the low latency and cost reduction. Machine learning is also shifting its role from the cloud to edge or tiny edge according to the paradigm shift. However, the fragmented and resource-constrained features of IoT devices have limited the development of artificial intelligence applications. Edge MLaaS (Machine Learning as-a-Service) has been studied to easily and quickly adopt machine learning to products and overcome the device limitations. This paper briefly summarizes what Edge MLaaS is and what element of research it requires.

• 전기전자학회논문지
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• 제19권1호
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• pp.45-51
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• 2015

최근 IoT(Internet of Things) 기기를 위한 근거리 무선 네트워크 시스템이 널리 활용되면서 점차 보안의 필요성이 증가하고 있다. 본 논문에서는 IEEE 802.15.4 호환 WPAN 기기를 위한 낮은 복잡도를 갖는 128-bit AES-$CCM^*$ 하드웨어를 효율적으로 구현하였다. WPAN 기기에서는 하드웨어 자원과 전력 소모가 매우 제한되기 때문에, 다양한 최적화 기법을 적용하여 낮은 복잡도를 갖는 AES-$CCM^*$ 하드웨어를 구현해야 한다. 본 논문은 하드웨어의 복잡도를 줄이기 위해 composite field 연산을 채택하면서 8-bit 데이터 패스를 갖는 folded AES processing core를 제안한다. 또한 IEEE 802.15.4 표준에서 정의된 $CCM^*$ 모드를 지원하기 위해 적은 하드웨어 자원을 사용하며 응답시간이 빠른 토글 구조의 AES-$CCM^*$ 제안한다. 본 논문에서 제안된 AES-$CCM^*$ 하드웨어는 기존의 하드웨어의 57%에 해당하는 게이트 수로 구현가능하다.

• International Journal of Internet, Broadcasting and Communication
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• 제13권1호
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• pp.20-25
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• 2021

In the background of the rapid development of the IoT, smart home work is becoming more and more important to each science and technology company. Smart home provides a safe, comfortable, high-quality, high-performance smart home living space compared to general homes, and at the same time It is responding to the low-carbon, eco-friendly global trend. Growth drivers driving the smart home market are increasing the number of Internet users, increasing disposable income in developing countries, increasing the importance of remote home monitoring, and increasing the need for energy saving and low carbon. In 2013-2014, Xiaomi launched a series of smart routers and smart home hardware devices. In 2015, it announced the latest product of the Xiaomi Ecological Chain, the "Smart Home Package," and in 2016 launched the MIJIA brand to invest in various smart product companies. In 2017, Xiaomi announced a plan to build an open smart hardware MIOT platform. We investigated the management strategy of Xiaomi home smart service based on IOT. The management strategy was divided into cost lead strategy, differentiation strategy of Xiaomi home service, and AIOT strategy of Xiaomi smart home.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.1011-1012
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• 2006

In this paper, implementation process of standard platform for T-DMB Receiver in low-cost and small-size are following: First, implement SoC for 32 bit RISC CPU and 16 bit DSP, Hardware H.264 CODEC, Post Processor or Video Display, Audio Processor, I/O Device. Second, implement Real Time OS for flexible application. Third, propose simple architecture for interface with peripheral devices using one-chip processor.

• 대한임베디드공학회논문지
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• 제13권5호
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• pp.253-259
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• 2018

Recently, small satellite industries are rapidly changing. Demand for high performance small satellites is increasing with the expansion of Earth Observation Satellite market. A next-generation small satellites require a higher resolution image storage capacity than before. However, there is a problem that the HW configuration of the existing small satellite image storage device could not meet these requirements. The conventional data storing system uses SDRAM to store image data taken from satellites. When SDRAM is used in small satellite platform of a next generation, there is a problem that the cost of physical space is eight times higher and satellite price is two times higher than NAND Flash. Using the same satellite hardware configuration for next-generation satellites will increase the satellite volume to meet hardware requirements. Additional cost is required for structural design, environmental testing, and satellite launch due to increasing volume. Therefore, in order to construct a low-cost, high-efficiency system. This paper shows a next-generation solid state recorder unit (SSRU) using MRAM and NAND Flash instead of SDRAM. As a result of this research, next generation small satellite retain a storage size and weight and improves the data storage space by 15 times and the storage speed by 4.5 times compare to conventional design. Also reduced energy consumption by 96% compared to SDRAM based storage devices.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 전력전자학술대회 논문집
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• pp.372-376
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• 2001

Due to several advantages of Pulse Width Modulation(PWM) Converter, such as unity power factor operation, elimination of low-order harmonics and regeneration of motor braking energy to source, the application range of PWM Converter has been rapidly extended in industrial application. Nowadays, vector control algorithm and space vector PWM(SVPWM) method are applied to improve the performances of PWM Converter, but vector control algorithm and SVPWM require to use Microprocessor and other digital devices in hardware, causing costly and somewhat large dimension system. In every practical application of energy conversion equipments, the design and implementation should be carried out considering cost and performance. High performance and low cost is the best choice for energy conversion equipments. So, this paper presents the practical design method and implementation results of 3-phase PWM Converter with analog hysteresis current controller, and verifies the performances of unit power factor operation and energy regeneration operation via experimental results.

• 산업기술연구
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• 제21권B호
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• pp.117-123
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• 2001

In a modern control field, a control engineer who has theoretical backgrounds with some practical knowledge is demanded. That is to say, an engineer who can understand and operate the various parts such as modeling, simulation, system analysis, signal processing, statistics, and hardware is required. In order to prove the theoretical backgrounds and operate various hardwares, a lot of experimental devices for students are designed in universities. Since the conventional experimental devices are manufactured abroad and the prices of the devices are too high, it is difficult to have. If a low cost experimental device can be developed, it will be very useful for a control engineering education. In Ibis paper, an experimental rig which has two control inputs and three sensor outputs to control the end point of a flexible beam is designed and manufactured. This rig can be used for a control field education.