• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.30.1-30.1
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• 2011

Silicon is one of useful materials in various industry such as semiconductor, solar cell, and secondary battery. The metallic silicon produces generally melting process for ingot type or chemical vapor deposition (CVD) for thin film type. However, these methods have disadvantages of high cost, complicated process, and consumption of much energy. Electrodeposition has been known as a powerful synthesis method for obtaining metallic species by relatively simple operation with current and voltage control. Unfortunately, the electrodeposition of the silicon is impossible in aqueous electrolyte solution due to its low oxidation-reduction equilibrium potential. Ionic liquids are simply defined as ionic melts with a melting point below $100^{\circ}C$. Characteristics of the ionic liquids are high ionic conductivities, low vapour pressures, chemical stability, and wide electrochemical windows. The ionic liquids enable the electrochemically active elements, such as silicon, titanium, and aluminum, to be reduced to their metallic states without vigorous hydrogen gas evolution. In this study, the electrodeposion of silicon has been investigated in ionic liquid of 1-butyl-3-methylpyrolidinium bis (trifluoromethylsulfonyl) imide ([bmpy]$Tf_2N$) saturated with $SiCl_4$ at room temperature. Also, the effect of electrode materials on the electrodeposition and morphological characteristics of the silicon electrodeposited were analyzed The silicon electrodeposited on gold substrate was composed of the metallic Si with single crystalline size between 100~200nm. The silicon content by XPS analysis was detected in 31.3 wt% and the others were oxygen, gold, and carbon. The oxygen was detected much in edge area of th electrode due to $SiO_2$ from a partial oxidation of the metallic Si.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.130-134
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• 2008

This paper presents a clock and data recovery(CDR) using a quarter-rate technique. The proposed CDR helps reduce the VCO frequency and is thus advantageous for high speed application. It can achieve a low jitter operation and extend the pull-in range without a reference clock. The CDR consists of a quarter-rate bang-bang type phase detector(PD) quarter-rate frequency detector(QRFD), two charge pumps circuits(CPs), low pass filter(LPF) and a ring voltage controlled oscillator(VCO). The Proposed CDR has been fabricated in a standard $0.18{\mu}m$ 1P6M CMOS technology. It occupies an active area $1{\times}1mm^2$ and consumes 98 mW from a single 1.8 V supply.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.9 no.3
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• pp.88-96
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• 1995

High speed elevator requires precise drive included in zero speed at start/stop drive for the high stability and controllability. The vector control techniques, which have been used for the precise operation of induction motor, can be divided into two classes; The indirect vector control by slip frequency and the direct vector control by field orientation. The existing direct vector control technique has a robustness against the change of motor parameter and the existing indirect vector control technique has a strength of control ability in the wide speed range comparatively. This study presents the DTIF (Direct Torque Indirect Flux) controller which has robust movement in the transition state and in about zero and low speed using the control technique in which torque is controlled by the direct vector technique and flux is controled by indirect vector technique. The proposed system is verified by simulation and experiment for driving 3 phase induction motor. The process of transition which is from about zero speed and low speed to high speed is compared and measured to specification of phase voltage, phase current and DC link current. It is verified that DTIF controller show robust and stable speed variation.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.373-373
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• 2014

Resistive-change random access memory (ReRAM) device is one of the promising candidates owing to its simple structure, high scalability potential and low power operation. Many resistive switching devices using transition metal oxides materials such as NiO, Al2O3, ZnO, HfO2, $TiO_2$, have attracting increased attention in recent years as the next-generation nonvolatile memory. Among various transition metal oxides materials, HfO2 has been adopted as the gate dielectric in advanced Si devices. For this reason, it is advantageous to develop an HfO2-based ReRAM devices to leverage its compatibility with Si. However, the annealing temperature of these high-k thin films for a suitable resistive memory switching is high, so there are several reports for low temperature process including microwave irradiation. In this paper, we demonstrate the bipolar resistive switching characteristics in the microwave irradiation annealing processed Ag/HfO2/Pt ReRAM device. Compared to the as-deposited Ag/HfO2/Pt device, highly improved uniformity of resistance values and operating voltage were obtained from the micro wave annealing processed HfO2 ReRAM device. In addition, a stable DC endurance (>100 cycles) and a high data retention (>104 sec) were achieved.

• Journal of Sensor Science and Technology
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• v.8 no.2
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• pp.163-170
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• 1999

A programmable A/D converter for an embedded fiber-optic combustion pressure sensor has been designed with 8 N and P channel MOSFETs, respectively. A local field enhancement for reducing programming voltage during writing as well as erasing an EEPROM device is introduced. In order to observe linear programmability of the EEPROM device during programming mode, a cell is developed with a $1.2\;{\mu}m$ double poly CMOS fabrication process in MOSIS. It is observed that the high resolution, of say 10mVolt, is valid in the range 1.25volts to 2volts. The experimental result is used for simulating the programmable 8 bit A/D converter with Hspice. The A/D converter is demonstrated to consume low power, $37\;{\mu}W$ by utilizing a programming operation. In addition, the converter is attained at the conversion frequency of 333 MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.66-71
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• 2014

This paper presents an analog front-end integrated circuit (IC) for medical ultrasound imaging systems using standard $0.18-{\mu}m$ CMOS process. The proposed front-end circuit includes the transmit part which consists of 15-V high-voltage pulser operating at 2.6 MHz, and the receive part which consists of switch and a low-power low-noise preamplifier. Depending on the operation mode, the output driver in the transmit pulser can be reconfigured as the switch in the receive path and thus the area of the overall front-end IC is reduced by over 70% in comparison to previous work. The designed single-channel front-end prototype consumes less than $0.045mm^2$ of core area and can be utilized as a key building block in highly-integrated multi-array ultrasound medical imaging systems.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.6
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• pp.587-593
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• 2011

A new high power density and low cost Photovoltaic Power Conditioning System (PV PCS) with energy storage system is proposed. Its high power density and cost effectiveness can be achieved through the unification of the maximum power point tracker and battery charger/discharger. Despite of the reduced power stage, the proposed system can achieve the same performances of maximum power point tracking and battery charging/discharging as the conventional system. Moreover, the high voltage stress across the link-capacitor can be relieved through the series-connected link-capacitor with the battery. Therefore, a large number of series/parallel-connected link-capacitors can be reduced by 4-times. Especially, when the utility power failure happens, both photovoltaic and battery energies can be supplied to the load with only one power stage. Therefore, it features a simpler structure, less mass, lower cost, and fewer devices. Finally, to confirm the operation, validity, and features of the proposed system, theoretical analysis and experimental results from a single phase AC 220Vrms/1.5kW prototype are presented.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.95-103
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• 2011

This paper proposes a 6b 1.2 GS/s 47.8 mW 0.17 $mm^2$ 65 nm CMOS ADC for high-rate wireless personal area network systems. The proposed ADC employs a source follower-free flash architecture with a wide input range of 1.0 $V_{p-p}$ at a 1.2 V supply voltage to minimize power consumption and high comparator offset effects in a nanometer CMOS technology. The track-and-hold circuits without source followers, the differential difference amplifiers with active loads in pre-amps, and the output averaging layout scheme properly handle a wide-range input signal with low distortion. The interpolation scheme halves the required number of pre-amps while three-stage cascaded latches implement a skew-free GS/s operation. The two-step bubble correction logic removes a maximum of three consecutive bubble code errors. The prototype ADC in a 65 nm CMOS demonstrates a measured DNL and INL within 0.77 LSB and 0.98 LSB, respectively. The ADC shows a maximum SNDR of 33.2 dB and a maximum SFDR of 44.7 dB at 1.2 GS/s. The ADC with an active die area of 0.17 $mm^2$ consumes 47.8 mW at 1.2 V and 1.2 GS/s.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.5
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• pp.1000-1006
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• 2007

This paper presents a power detector circuit which monitors the transmitting power for the application in CDMA cell phones. The proposed power detector are composed of coupler for coupling output power and detector fur monitoring output power. The designed coupler has low loss characteristic because it adopts the stripline structure which consists of two ground planes at both sides of signal plane. The design frequency is 824-849MHz which is the Tx band fur CDMA mobile terminal, and the coupling factor of the stripline coupler is -20dB. A schottky barrier diode is adopted for detector design because of its high speed operation with minimized loss. The required impedance matching is performed to improve the linearity and sensitivity of output voltage at relatively low detector input level where the nonlinear characteristic of diode exists. The package parasitics as well as intrinsic diode model are considered for simulation of the detector. The predicted performances agree well with the measured results.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.1
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• pp.91-97
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• 2014

Recently, the LED(Light Emitting Diode) is expected to replace conventional lamps including incandescent, halogen and fluorescent lamps for some general illumination application, due to some obvious features such as high luminous efficiency, safety, long life, environment-friendly characteristics and so on. To drive the LED, a single stage PFC(Power Factor Correction) flyback converter has been adopted to satisfy the isolation, PFC and low cost. The conventional flyback LED driver has the serious disadvantage of high 120Hz output current ripple caused by the PFC operation. To overcome this drawback, a new PFC flyback with low 120Hz output current ripple is proposed in this paper. It is composed of 2 power stages, the DCM(Discontinuous Conduction Mode) flyback converter for PFC and BCM(Boundary Conduction Mode) boost converter for tightly regulated LED current. Since the link capacitor is located in the secondary side, its voltage stress is small. Moreover, since the driver is composed of 2 power stages, small output filter and link capacitor can be used. Especially, since the flyback is operated at DCM, the PFC can be automatically obtained and thus, an additional PFC IC is not necessary. Therefore, only one control IC for BCM boost converter is required. To confirm the validity of the proposed converter, theoretical analysis and experimental results from a prototype of 24W LED driver are presented.