• Applied Biological Chemistry
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• v.34 no.2
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• pp.187-189
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• 1991

Gelatinization temperatures of upland and lowland waxy brown rice starches annealed at $25^{\circ}C$ and $60^{\circ}C$ for 24hr were investigated with differential scanning calorimetry No annealing effect was observed at low temperature. The upland rice starch showed narrower range of gelatinization temperature upon annealing treatment at $60\circ}C$ compared with the lowland rice starch. The enthalpy of gelatinization was not changed in case of the upland rice starch but was increased in case of the lowland one upon annealing.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.290.2-290.2
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• 2016

Recently, organic thin-film transistors have been widely researched for organic light-emitting diode panels, memory devices, logic circuits for flexible display because of its virtue of mechanical flexibility, low fabrication cost, low process temperature, and large area production. In order to achieve high performance OTFTs, increase in accumulation carrier mobility is a critical factor. Post-fabrication thermal annealing process has been known as one of the methods to achieve this by improving the crystal quality of organic semiconductor materials In this paper, we researched the properties of pentacene films with X-Ray Diffraction (XRD) and Atomic Force Microscope (AFM) analyses as different annealing temperature in N2 ambient. Electrical characterization of the pentacene based thin film transistor was also conducted by transfer length method (TLM) with different annealing temperature in Al- and Ti-pentacene junctions to confirm the Fermi level pinning phenomenon. For Al- and Ti-pentacene junctions, is was found that as the surface quality of the pentacene films changed as annealing temperature increased, the hole-barrier height (h-BH) that were controlled by Fermi level pinning were effectively reduced.

• Journal of the Semiconductor & Display Technology
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• v.16 no.1
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• pp.97-101
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• 2017

In this paper, IGZO thin film transistor (TFT) was fabricated with cross-linked Poly (4-vinylphenol) (PVP) gate dielectric for flexible, transparent display applications. The PVP is one of the candidates for low-temperature gate insulators. MIM structure was fabricated to measure the leakage current and evaluate the insulator properties according to the annealing temperature. Low leakage current ( <0.1nA/cm2 @ 1MV/cm ) was observed at $200^{\circ}C$ annealing condition and decreases much more as the annealing temperature increases. The electrical characteristics of IGZO TFT such as subthreshold swing, mobility and ON/OFF current ratio were also improved, which shows that the performance of IGZO TFTs with PVP can be enhanced by reducing the amount of incomplete crosslinking in PVP.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1997.06a
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• pp.231-236
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• 1997

To improve electrical properties and uniformity of high-low doped n-type GaAs, new ohmic contacts with a low-resistance and the superior uniformity was developed using a concept of hybrid ohmic contact. The hybrid ohmic contact displayed good surface and interface morphology and had minimum contact resistivity of 3${\times}$10-6 $\Omega$$\textrm{cm}^2$ in a wide annealing temperature ranged from 340$^{\circ}C$ to 420$^{\circ}C$, which was much wider than that of conventional ohmic contacts. The microstructural analysis showed that the Pd/Ge ohmic contact at low annealing temperature (∼300$^{\circ}C$) and also annealing temperature (∼400$^{\circ}C$), resulting ij hybrid ohmic contacts.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.11
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• pp.859-863
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• 2010

Evolution of surface morphology of ${\alpha}-Al_2O_3$ substrate was investigated as a function of annealing temperature and time. Commercial (0001) ${\alpha}-Al_2O_3$ single crystal substrates were annealed in the range of $600-1000^{\circ}C$ in air. At $600^{\circ}C$, step-terrace structure started to be formed on the substrate. However, the surface roughness on the terrace was still considerable and a number of islands were observed on the step edges as well as the terraces. As the annealing temperature increased, the islands were absorbed into the step edges. Thus the terraces were smoother and the step edges were more straightened. Well-defined surface with a step height of 0.2 nm was formed above $900^{\circ}C$. On the other hand, when the substrate was annealed at a fixed temperature of $1000^{\circ}C$, the change of surface morphology was observed for the substrate annealed for 10 min. After the annealing for 30 min, the surface on which any islands could not survive was observed.

• Journal of the Korean institute of surface engineering
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• v.52 no.6
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• pp.306-309
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• 2019

Titanium (Ti) doped indium oxide (In₂O₃) films were deposited on glass substrates by RF magnetron sputtering and the films were rapid thermal annealed at 100, 200, and 300℃, respectively to investigate the influence of the rapid annealing on the opto-electrical performance of the films. The grain size of In₂O₃ (222) plane increased with annealing temperatures and their electrical resistivity decreased to as low as 8.86×10^-4 Ωcm at 300℃. The visible transmittance also improved from 77.1 to 79.5% when the annealing temperature increased. The optical band gap of the TIO films shifted from 4.010 to 4.087 eV with increases in annealing temperature from room temperature to 300℃. The figure of merit shows that the TIO films annealed at 300℃ had better optical and electrical performance than the other films prepared using lower-temperature or no annealing.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.34-38
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• 1992

Low temperature device processing has become of great interest within the last few years. In such low temperature processes, SiO$_2$films formed by Plasma-enhanced chemical vapor deposition (PECVD) have been studied. PECVD SiO$_2$films were formed with substrate temperature, and annealing time and temperature of RTP changed, and its'characteristics were obsreved by C-V measurement. We found that the quality of SiO$_2$films formed by PECVD depended on annealing time rather than substrate temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.725-728
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• 2001

We have fabricated thin films using the DC/RF magnetron sputtering of 74wt%Ni-l8wt%Cr-4wt%Al-4wt%Cu alloy target and studied the effect of the process parameters on the electrical properties for low TCR(Temperature Coefficient of Resistance) films. In sputtering process, pressure, power and substrate temperature, are varied as controllable parameter. The films are annealed to 400$^{\circ}C$ in air and nitrogen atmosphere. The sheet resistance, TCR of the films increases with increasing annealing temperature. It abruptly increased as annealing temperature increased over 300$^{\circ}C$ in air atmosphere. From XRD, it is found that these results are due to the existence of NiO on film surface formed by annealing. As a results of them, TCR can be controlled by variation of sputter process parameter and annealing of thin film.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.4
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• pp.568-573
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• 1996

The amorphous silicon films deposited by low pressure chemical vapor deposition are crystallized by the various annealing techniques including low-temperature furnace annealing and two-step annealing. Two-step annealing is the combination of furnace annealing at 600 [.deg. C] for 24 h and the sequential furnace annealing at 950 [.deg. C] 1h or the excimer laser annealing. It s found that two-step annealings reduce the in-grain defects significantly without changing the grain boundary structure. The performance of the poly-Si thin film transistors (TFTs) produced by employing the tow-step annealing has been improved significantly compared with those of one-step annealing. (author). 13 refs., 6 figs., 1 tab.

• Korean Journal of Materials Research
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• v.13 no.6
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• pp.398-403
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• 2003

Shallow $p^{＋}$ n junction was formed using a ULE(ultra low energy) implanter. Deactivation phenomena were investigated for the shallow source/drain junction based on measurements of post-annealing time and temperature following the rapid thermal annealing(RTA) treatments. We found that deactivation kinetics has two regimes such that the amount of deactivation increases exponentially with annealing temperature up to $850^{\circ}C$ and that it decreases linearly with the annealing temperature beyond that temperature. We believe that the first regime is kinetically limited while the second one is thermodynamically limited. We also observed "transient enhanced deactivation", an anomalous increase in sheet resistance during the early stage of annealing at temperatures higher than X$/^{\circ}C$. Activation energy for transient enhanced deactivation was measured to be 1.75-1.87 eV range, while that for normal deactivation was found to be between 3.49-3.69 eV.