• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.19.1-19.1
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• 2009

Phase change random access memory (PRAM)은 large sensing signal margin, fast programming speed, low operation voltage, high speed operation, good data retention, high scalability등을 가지는 가장 유망한 차세대 비휘발성 메모리이다. 현재 PRAM용 상변화 재료로는 주로 Ge2Sb2Te5가 사용되고 있지만 reset 전류가 높고 reliability 가 좋지 않아서 새로운 상변화 물질 연구가 필요하다. AgInSbTe (AIST)는 GST와 더불어 열에 의한 가역적 상변화를 하는 소재로 광기록 매체에서는 기록 속도가 빠르고 동작 특성이 우수하다는 특징이 있다. 본 연구에서는 XRD, 비저항측정등을 통해 온도에 따른 AIST의 물성 및 결정화 특성을 분석하고 나노 소자제작을 통해 그 전기적 특성을 평가하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.22-28
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• 2009

As multiprocessors have been widely adopted in embedded systems, task computation energy consumption should be minimized with several low power techniques supported by the multiprocessors. This paper proposes an energy-aware task scheduling algorithm that adopts both dynamic voltage scaling and power shutdown in multiprocessor environments. Considering the timing and energy overhead of power shutdown, the proposed algorithm performs an iterative task assignment and task ordering for multiprocessor systems. In this case, the iterative priority-based task scheduling is adopted to obtain the best solution with the minimized total energy consumption. Total energy consumption is calculated by considering a linear programming model and threshold time of power shutdown. By analyzing experimental results for standard task graphs based on real applications, the resource and timing limitations were analyzed to maximize energy savings. Considering the experimental results, the proposed energy-aware task scheduling provided meaningful performance enhancements over the existing priority-based task scheduling approaches.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.128-133
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• 2008

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90nm technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.

• Proceedings of the KOSOMBE Conference
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• v.1998 no.11
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• pp.191-192
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• 1998

We report on the design of a low-noise 40 channel SQUID system for biomagnetism. We used low-noise SQUID sensor with the pickup coil integrated on the same wafer as the SQUID. The SQUID electronics were simplified by increasing the voltage output of the SQUID. The SQUID insert was designed to have low thermal load, minimizing the liquid helium loss. The digital signal processing provides versatile analysis tools and the software is based on the object-oriented programming. For the effective localization of the source location, solutions of the inverse problems based on the lead-field and the simulated anneal ins were studied.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.1
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• pp.33-41
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• 2019

We propose an embedded solution to design a high-speed and high-accuracy 16bit analog-digital signal processing interface for the control systems using various external analog signals. Choosing TMS320F28377D micro controller unit (MCU) featuring high-performance processing in the 32-bit floating point operation, low power consumption, and various I/O device supports, we design and build the proposed system that supports both 16-bit analog-digital converter (ADC) interface and high precision digital-analog converter (DAC) interface. The ADC receives voltage-level differential signals from fully differential amplifiers, and the DAC communicates with MCU through 50 MHz bandwidth high-fast serial peripheral interface (SPI). We port the boot loader and device drivers to the implemented board, and construct the firmware development environment for the application programming. The performance of the entire implemented system is demonstrated by analog-digital signal processing tests, and is verified by comparing the test results with those of existing similar systems.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.35-38
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• 2002

In this paper, the characteristics of channel hot electron (CHE) injection for the write operation in a NOR-type SONOS flash memory with common source line were investigated. The thicknesses of he tunnel oxide, the memory nitride， and the blocking oxide layers for the gate insulator of the fabricated SONOS devices were $34{\AA}$, $73{\AA}$, and $34{\AA}$, respectively. The SONOS devices compared to floating gate devices have many advantages, which are a simpler cell structure, compatibility with conventional logic CMOS process and a superior scalability. For these reasons, the introduction of SONOS device has stimulated. In the conventional SONOS devices, Modified Folwer-Nordheim (MFN) tunneling and CHE injection for writing require high voltages, which are typically in the range of 9 V to 15 V. However CHE injection in our devices was achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The memory window of about 3.2 V and the write speed of $100{\mu}s$ were obtained. Also, the disturbance and drain turn-on leakage during CHE injection were not affected in the SONOS array. These results show that CHE injection can be achieved with a low voltage and single power supply, and applied for the high speed program of the SONOS memory devices.

• Journal of the Korean Society of Safety
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• v.36 no.5
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• pp.10-17
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• 2021

The controversy over the risk of the human body being affected by electromagnetic fields emitted from 60 Hz power lines continues without end. There are currently no new studies or research progress being made in this direction that is notable, and the number of civil complaints is gradually increasing. The problem is that each study produces different results, among which the effect of exposure to magnetic fields on childhood leukemia is a major one. In Korea, an electrician who was maintaining a 22.9 kV power line died of leukemia, which has recently been recognized as an occupational disease. Methods to reduce magnetic fields from power lines include shielding with wire loops, incorporating split phases and compaction techniques, installing underground power lines, converting to high-voltage direct current (HVDC), and increasing the ground clearance of transmission towers. Depending on whether a separate power supply is needed or not, there are two types of wire loops: passive loop and active loop. Magnetic field reduction is currently done through underground power lines; however, the disadvantage of this process is high construction costs. Installing passive loops, with relatively low construction costs, leads to lower magnetic field reduction rates than installing underground cables and a weakness to not solving the landscape problem. This methodological study aims at designing methods and reducing the effects of 2-wire set loops-the simplest and most practical. Since the method proposed in this study has been designed after analyzing the distribution of complex electromagnetic fields near the expected loop installation location, a practical design can be implemented without the need for any difficult optimization programming.