• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.151-151
• /
• 2010

In this paper, the electrically properties of nonvolatile memory (NVM) using multi-stacks gate insulators of oxide-nitride-oxynitride (ONOn) and active layer of the low temperature polycrystalline silicon (LTPS) were investigated. From hydrogenated amorphous silicon (a-Si:H), the LTPS thin films with high crystalline fraction of 96% and low surface's roughness of 1.28 nm were fabricated by the metal induced crystallization (MIC) with annealing conditions of $650^{\circ}C$ for 5 hours on glass substrates. The LTPS thin film transistor (TFT) or the NVM obtains a field effect mobility of ($\mu_{FE}$) $10\;cm^2/V{\cdot}s$, threshold voltage ($V_{TH}$) of -3.5V. The results demonstrated that the NVM has a memory window of 1.6 V with a programming and erasing (P/E) voltage of -14 V and 14 V in 1 ms. Moreover, retention properties of the memory was determined exceed 80% after 10 years. Therefore, the LTPS fabricated by the MIC became a potential material for NVM application which employed for the system integration of the panel display.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2016.02a
• /
• pp.324-326
• /
• 2016

In this study, we have investigated indium tin zinc oxide (ITZO) as an active channel for non-volatile memory (NVM) devices. The electrical and memory characteristics of NVM devices using multi-stack gate insulator SiO2/SiOx/SiOxNy (OOxOy) with Si-rich SiOx for charge storage layer were also reported. The transmittance of ITZO films reached over 85%. Besides, ITZO-based NVM devices showed good electrical properties such as high field effect mobility of 25.8 cm2/V.s, low threshold voltage of 0.75 V, low subthreshold slope of 0.23 V/dec and high on-off current ratio of $1.25{\times}107$. The transmission Fourier Transform Infrared spectroscopy of SiOx charge storage layer with the richest silicon content showed an assignment at peaks around 2000-2300 cm-1. It indicates that many silicon phases and defect sources exist in the matrix of the SiOx films. In addition, the characteristics of NVM device showed a retention exceeding 97% of threshold voltage shift after 104 s and greater than 94% after 10 years with low operating voltage of +11 V at only 1 ms programming duration time. Therefore, the NVM fabricated by high transparent ITZO active layer and OOxOy memory stack has been applied for the flexible memory system.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.427-427
• /
• 2012

Ferroelectric-gate field effect transistor based memory using a nanowire as a conducting channel offers exceptional advantages over conventional memory devices, like small cell size, low-voltage operation, low power consumption, fast programming/erase speed and non-volatility. We successfully fabricated ferroelectric nonvolatile memory devices using both n-type and p-type Si nanowires coated with organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] via a low temperature fabrication process. The devices performance was carefully characterized in terms of their electrical transport, retention time and endurance test. Our p-type Si NW ferroelectric memory devices exhibit excellent memory characteristics with a large modulation in channel conductance between ON and OFF states exceeding $10^5$; long retention time of over $5{\times}10^4$ sec and high endurance of over 105 programming cycles while maintaining ON/OFF ratio higher $10^3$. This result offers a viable way to fabricate a high performance high-density nonvolatile memory device using a low temperature fabrication processing technique, which makes it suitable for flexible electronics.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.27 no.10
• /
• pp.93-100
• /
• 2013

Generally, the conventional battery charging system using an analog method has the large, heavy hardware and low efficiency. Also, it has the disadvantage that it is necessary to replace the control circuit on the basis of the characteristic curve of the specific battery cell. The proposed programmable digital LLC resonant charging system use high efficiency control system(CC-CV), and has characteristic a small hardware and advantage that a digital programming of the voltage, current, and battery capacity characteristics can be flexible. The system proposed the use of Half-bridge LLC resonant converter is possible to improve efficiency and reduce switching losses by using ZVS topology. Further, a constant voltage - constant current(CC-CV) control algorithm apply to the charger which using a buck converter. The performance of the proposed system is demonstrated through experiments.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.388-388
• /
• 2012

In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.7 no.5
• /
• pp.1061-1066
• /
• 2012

A digital memory has been widely used as a device for storing information due to its reliable, fast and relatively simple control circuit. However, the storage of the digital memory will be limited by the inablility to make smaller linewidths. One way to dramatically increase the storeage capability of the memory is to change the type of stored data from digital to analog. The analog memory fabricated in a standard single poly 0.6um CMOS process has been developed. Single cell and adjacent circuit block for programming have been designed and characterized. Applications include low-density non-volatile memory, control of redundancy in SRAM and DRAM memories, ID or security code registers, and image and sound memory.

• Journal of Sensor Science and Technology
• /
• v.4 no.3
• /
• pp.80-88
• /
• 1995

This paper presents the fabrication of a metal-insulator-metal(MIM) antifuse structure consisting of insulators sandwiched between top electrode, Al, and bottom electrode, TiW and additionally studies on antifuse properties depending on the condition of insulator. The intermetallic insulators, prepared by means of sputter, comprised of silicon oxide and tantalum oxide. In such an antifuse structure, silicon oxide layer is utilized to decrease the leakage current and tantalum oxide layer, of which the dielectric strength is lower than that of silicon oxide, is also utilized to lower the breakdown voltage near 10V. Finally sufficient low leakage current, below 1nA, and low programming voltage, about 9V, could be obtained in antifuse device comprising $Al/Ta_{2}O_{5}(10nm)/SiO_{2}(10nm)/TiW$ structure and OFF resistance of 3$3.65M{\Omega}$ and ON resistance of $7.26{\Omega}$ could be also obtained. This $Ta_{2}O_{5}/SiO_{2}$ based antifuse structures will be promising for highly reliable programmable device.

• Journal of Electrical Engineering and Technology
• /
• v.10 no.4
• /
• pp.1389-1399
• /
• 2015

This research suggests maximum power point tracking (MPPT) for the solar photovoltaic (PV) power scheme using a new constant voltage (CV) fractional order incremental conductance (FOINC) algorithm. The PV panel has low transformation efficiency and power output of PV panel depends on the change in weather conditions. Possible extracting power can be raised to a battery load utilizing a MPPT algorithm. Among all the MPPT strategies, the incremental conductance (INC) algorithm is mostly employed due to easy implementation, less fluctuations and faster tracking, which is not only has the merits of INC, fractional order can deliver a dynamic mathematical modelling to define non-linear physiognomies. CV-FOINC variation as dynamic variable is exploited to regulate the PV power toward the peak operating point. For a lesser scale photovoltaic conversion scheme, the suggested technique is validated by simulation with dissimilar operating conditions. Contributions are made in numerous aspects of the entire system, including new control algorithm design, system simulation, converter design, programming into simulation environment and experimental setup. The results confirm that the small tracking period and practicality in tracking of photovoltaic array.

• Proceedings of the KIEE Conference
• /
• 1992.07b
• /
• pp.1088-1091
• /
• 1992

Programmed PWM(Pulse Width Modulated) generation techniques eliminating several low order harmonics have been widely used in the inverter circuit which produces minimum current ripple, reduced torque pulsation and thereby improves overall system performance. However, the applications of the programmed PWM technique are limited to CVCF(Constant Voltage Constant Frequency) applications and various motor drives. Although the programmed PWM produces a lower harmonic distorted waveform than the carrier modulated PWM, real-time programming is not possible because of the complicated calculation required for the gating signal. In this paper, a new programmed PWM technique named TAM (time averaging model) is developed to compensate for the demerits of the conventional programmed PWM technique with moderate harmonic distortion. Computer simulations are performed to verify the performance of the proposed algorithm.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2006.08a
• /
• pp.413-418
• /
• 2006

Highly stable thin-film transistor (TFT) pixel employing both low temperature polycrystalline silicon (LTPS) and amorphous silicon (a-Si) for active matrix organic light emitting diode (AMOLED) is discussed. ELA (excimer laser annealing) LTPS-TFT pixel should compensate $I_{OLED}$ variation caused by the non-uniformity of LTPS-TFT due to the fluctuation of excimer laser energy and amorphous silicon TFT pixel is desired to suppress the decrease of $I_{OLED}$ induced by the degradation of a-Si TFT. We discuss various compensation schemes of both LTPS and a-Si TFT employing the voltage and the current programming.