• Title/Summary/Keyword: Low power systems

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Status and issues of CAD/CAM technology in Korea (국내 CAD/CAM 현황과 문제점)

  • 이종원;김태수
    • 제어로봇시스템학회:학술대회논문집
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    • 1986.10a
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    • pp.437-442
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    • 1986
  • Survey has been made to evaluate technological level and to identify research issues in CAD/CAM area. It is found out that major users of the CAD/CAM system are in mechanical and electronics as well as garment industries. Their experience shows that the impact of the CAD/CAM introduction is not yet noticeable in drafting man power and cost reduction. It is identified that the low penetration rate of CAD/CAM technology in industry is due to the lack of locally developed CAD/CAM softwares.

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New Zero-Current-Switching PWM Converters with Low Switching Loss (손실을 최소화한 새로운 영전류 스위칭 방식의 PWM 컨버터)

  • Ma, Keun-Su;Kim, Yang-Mo
    • Proceedings of the KIEE Conference
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    • 2000.07b
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    • pp.1193-1195
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    • 2000
  • In conventional zero-current-switching(ZCS) PWM converters, the switching loss, stress and noise can't be minimized because they adopt auxiliary switches operated in hard-switching. In this paper, new ZCS-PWM converters of which auxiliary switches always operate with soft-switching are proposed. Therefore, the proposed ZCS-PWM converters are most suitable for systems requiring high-power density. The characteristics of these converters are verified by results of simulation.

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Simulink Model of 3-Phase Diode Rectifiers (3상 다이오드 정류기의 Simulink 모델)

  • Lee Jin-Woo
    • Proceedings of the KIPE Conference
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    • 2001.07a
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    • pp.514-519
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    • 2001
  • Most of inverters adopt a diode rectifier as an input stage, which has very simple and rugged structure and therefore low cost. In order to properly design the 3-phase diode rectifier with an output smoothing capacitor and input inductors, it is necessary to fully simulate the system due to its nonlinear characteristics. Therefore this paper describes the operating behaviors including the current commutation in detail by using the proposed equivalent circuit, and also proposes the Simulink-based model of the system. The simulation results show the validity of the proposed model in all operating conditions.

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A Selective Usage of Page Cache towards Low-Power Systems (저전력 시스템을 위한 선택적 페이지 캐쉬 사용 기법)

  • 송형근;차호정
    • Proceedings of the Korean Information Science Society Conference
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    • 2003.04a
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    • pp.208-210
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    • 2003
  • 본 논문은 내장형 시스템에서 저전력 소모를 위한 선택적 페이지 캐쉬 사용 기법을 제안한다. 내장형 시스템의 저장매체로 널리 사용되고 있는 플래쉬 메모리는 데이터를 압축하여 저장하기 때문에 리눅스에서 사용되는 페이지 캐쉬가 효과적으로 동작한다. 하지만 플래쉬 메모리는 RAM 보다 전력 소모가 적기 때문에 페이지 캐쉬 사용에 따른 빈번한 RAM 접근 횟수는 전력 소모량을 증가시킨다. 따라서 저전력 시스템 운영을 위해서 페이지 캐쉬를 선택적으로 사용하는 것을 제안한다. 리눅스 운영체제상에서 구현된 시스템을 바탕으로 수행속도가 향상되고 전력 소모량이 감소함을 보인다.

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Low-Power Liquid Crystal Display Systems using DLS (Dynamic Backlight Luminance Scaling) (동적 후면조명 밝기 조정 (DLS)을 이용한 저전력 LCD시스템 구현 기법)

  • 최인석;장래혁
    • Proceedings of the Korean Information Science Society Conference
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    • 2003.04a
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    • pp.139-141
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    • 2003
  • 최근의 휴대용 시스템에서는 디스플레이로 투과형 LCD를 주로 채택하고 있다. 투과형 LCD는 후면조명이 광원이 되는데, 후면조명(Backlight)의 소비전력이 시스템 전체 소비 전력에서 큰 비중을 차지한다. 우리는 화질의 큰 저하 없이 후면조명의 소비 전력을 줄이는 방법인 DLS를 소개한다. 본 논문에서는 DLS 구현과 구현한 플랫폼에서의 실험결과를 간단히 언급한다.

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DDC-Based Control of Display Systems for Low-Power Consumption (저소비 전력을 위한 DDC기반의 디스플레이 시스템 제어)

  • 임현식;이인환
    • Proceedings of the Korean Information Science Society Conference
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    • 2004.10a
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    • pp.673-675
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    • 2004
  • 컴퓨터 시스템의 구성 요소인 디스플레이 시스템은 가장 많은 전력을 소모하는 장치이다. 디스플레이 시스템의 전력을 효과적으로 줄이기 위하여 이미지 제어, 주파수 제어 등이 있지만 가장 효과적인 것은 LCD 패널부와 백라이트(backlight)를 제어하는 것이다. 본 논문에서는 디스플레이 시스템에서 DDC(Display Data Channel)를 이용하여 패널과 백 라이트 전압 레벨을 조절하여 저전력을 구현하였다. 호스트(PC)에서 동작하는 응용프로그램의 작성과 호스트의 영령을 받아 처리할 수 있는 디스플레이부를 구현하였다. 데스크탑 컴퓨터와 15, 17인치 LCD(Liquid Crystal Display) 모니터에서 소비 전력을 측정하였으며, 2-86%정도의 소비 전력을 줄이는 결과를 확인하였다.

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A Study on a Ku-Band High Power and High Efficiency Radial Combiner (Ku 대역 고출력 고효율 Radial Combiner에 대한 연구)

  • Yun, Song-Hyun;Kim, Si-Ok;Lee, Su Hyun;Lim, Byeong-Ok;Lee, Bok-Hyung;Jeon, Yong-Kyu;Kim, Hyun-Kyu;Yoo, Young-Geun
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.28 no.5
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    • pp.400-409
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    • 2017
  • We have studied a combiner that can withstand high power while minimizing insertion loss in high frequency band. In particularly, because the output power that can be output per unit elements is much lower in the Ku band and above than in the low frequency band, it is necessary to combine many semiconductor elements in order to make a high power SSPA. A planar combiner such as a microstrip, as the number of elements to be combined increases, the insertion loss increases proportionally, resulting in a reduction in the overall system efficiency and an increase heating value also. The planar combiner also have some problems due to the low power handling rate. To improve these problems, we proposed a Cavity Radial Combiner. A Ku band 16-way Cavity Radial Combiner was fabricated and measured. As a result, it was tested 14dB return loss and over 94.5 % output combining efficiency in design band.

A Dual Charge Pump PLL-based Clock Generator with Power Down Schemes for Low Power Systems (저 전력 시스템을 위한 파워다운 구조를 가지는 이중 전하 펌프 PLL 기반 클록 발생기)

  • Ha, Jong-Chan;Hwang, Tae-Jin;Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.11
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    • pp.9-16
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    • 2005
  • This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

Simulation Experiment of PEMFC Using Insulation Vessel at Low Temperature Region (저온영역에서 단열용기를 이용한 연료전지 모의 실험)

  • Jo, In-Su;Kwon, Oh-Jung;Kim, Yu;Hyun, Deok-Su;Park, Chang-Kwon;Oh, Byeong-Soo
    • Transactions of the Korean hydrogen and new energy society
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    • v.19 no.5
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    • pp.403-409
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    • 2008
  • Polymer electrolyte membrane fuel cell (PEMFC) is very interesting power source due to high power density, simple construction and operation at low temperature. But it has problems such as high cost, improvement of performance, effect of temperature and initial start at low temperature. These problems can be approached to be solved by using experiment and mathematical method which are general principles for analysis and optimization of control system for heat and hydrogen detecting management. In this paper, insulation vessel and control system for stable operation of fuel cell at low temperature were developed for experiment. The constant temperature capability and the heating time at sub-zero temperatures with insulation control system were studied by using a heating bar of 60W class. PEMFC stack which was made by 4 cells with $50\;mc^2$ active area in each cell is a thermal source. Times which take to reach constant temperature by the state of insulation vacuum were measured at variable environment temperatures. The test was performed at two conditions: heating mode and cooling mode. Constant temperature capability was better at lower environment temperature and vacuum pressure. The results of this experiment could be used as basis data about stable operation of fuel cell stack in low temperature zone.

Design of an Active Inductor-Based T/R Switch in 0.13 μm CMOS Technology for 2.4 GHz RF Transceivers

  • Bhuiyan, Mohammad Arif Sobhan;Reaz, Mamun Bin Ibne;Badal, Md. Torikul Islam;Mukit, Md. Abdul;Kamal, Noorfazila
    • Transactions on Electrical and Electronic Materials
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    • v.17 no.5
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    • pp.261-269
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    • 2016
  • A high-performance transmit/receive (T/R) switch is essential for every radio-frequency (RF) device. This paper proposes a T/R switch that is designed in the CEDEC 0.13 μm complementary metal-oxide-semiconductor (CMOS) technology for 2.4 GHz ISM-band RF applications. The switch exhibits a 1 dB insertion loss, a 28.6 dB isolation, and a 35.8 dBm power-handling capacity in the transmit mode; meanwhile, for the 1.8 V/0 V control voltages, a 1.1 dB insertion loss and a 19.4 dB isolation were exhibited with an extremely-low power dissipation of 377.14 μW in the receive mode. Besides, the variations of the insertion loss and the isolation of the switch for a temperature change from - 25℃ to 125℃ are 0.019 dB and 0.095 dB, respectively. To obtain a lucrative performance, an active inductor-based resonant circuit, body floating, a transistor W/L optimization, and an isolated CMOS structure were adopted for the switch design. Further, due to the avoidance of bulky inductors and capacitors, a very small chip size of 0.0207 mm2 that is the lowest-ever reported chip area for this frequency band was achieved.