• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.7
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• pp.815-823
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• 1999

This study considers an implementation of artificial neural networks to the receding horizon optimal control and is applications to power systems. The Generalized Backpropagation-Through-Time (GBTT) algorithm is presented to deal with a quadratic cost function defined in a finite-time horizon. A decentralized approach is used to control the complex global system with simpler local controllers that need only local information. A Neural network based Receding horizon Optimal Control (NROC) 1aw is derived for the local nonlinear systems. The proposed NROC scheme is implemented with two artificial neural networks, Identification Neural Network (IDNN) and Optimal Control Neural Network (OCNN). The proposed NROC is applied to a power system to improve the damping of the low-frequency oscillation. The simulation results show that the NROC based power system stabilizer performs well with good damping for different loading conditions and fault types.

• Journal of the Korea Society of Computer and Information
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• v.23 no.11
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• pp.67-74
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• 2018

The verification for the design limit margin of the power device for the information communication and surveillance systems using HALT(Highly Accelerated Life Test) reliability test is described. The HALT reliability test performs with a step stress method which change condition until the marginal step in a design and development phase. The HALT test methods are the low temperature(cold) step stress test, the high temperature(hot) step stress test, the thermal shock cyclic stess test, and the high temperature destruct limit(hot DL) step stress test. The power device is checked the operating performance during the test. In this paper, the HALT was performed to find out the design limit margin of the power device.

• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1046-1052
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• 2017

The load on the power grid of South Korea is expected to grow continuously until the late 2020s, and it is necessary to increase the transfer capacity from the Eastern grid to the Seoul-Gyeonggi region by reinforcing the transmission network for the electric power system to remain stable. To this end, the grid reinforcement by two bipole LCC HVDC transmission systems have been considered on account of the public acceptability and high growth of the fault current level, even though an additional 765kV system construction is more economical. Since the probability of the existing 765kV double circuit transmission line trip is extremely low, a dynamic simulation study was carried out to estimate the efficient HVDC capacity able to stabilize the transient stability by utilizing the HVDC overload capability. This paper suggests the application plan to reduce the HVDC construction capacity with ensuring the transient stability during the 765kV line trip.

• Journal of Power Electronics
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• v.11 no.3
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• pp.304-310
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• 2011

The power series approximation method is proposed for real time implementations of a discrete flux observer. The proposed method improves the performance of the discrete flux observer in the case of a low sampling rate and high speed range, where the simple discrete flux observer converted by the Euler method cannot estimate the actual flux precisely. The performance of discrete flux observers with different orders of approximation is compared to find out the proper order of approximation. The validity of the proposed method is verified through simulation and experiment.

• Journal of Power Electronics
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• v.11 no.2
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• pp.188-193
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• 2011

A highly efficient AC-DC converter for small wind power generation systems using a brushless DC generator (BLDCG) is presented in this paper. The market standard AC-DC converter for a BLDCG consists of a three-phase diode rectifier and a boost DC-DC converter, which has an IGBT and a fast recovery diode (FRD). This kind of two-stage solution basically suffers from a large amount of conduction loss and the efficiency greatly decreases under a light load, or at a low current, because of the switching devices with a P-N junction. In order to overcome this low efficiency, especially at a low current, a three-phase bridgcless converter consisting of three upper side FRDs and three lower side Super Junction FETs is presented. In the overall operating speed region, including the cut-in speed, the efficiency of the proposed converter is improved by up to 99%. Such a remarkable result is validated and compared with conventional solutions by calculating the power loss based on I-V curves and the switching loss data of the adopted commercial switches and the current waveforms obtained through PSIM simulations.

• Smart Structures and Systems
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• v.14 no.4
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• pp.617-641
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• 2014

The energy constraint is still a common issue for the practical application of wireless sensors, since they are usually powered by batteries which limit their lifetime. In this paper, a practical compound energy efficiency strategy is proposed and realized in the implementation of a real time wireless sensor platform. The platform is intended for wireless structural monitoring applications and consists of three parts, wireless sensing unit, base station and data acquisition and configuration software running in a computer within the Matlab environment. The high energy efficiency of the wireless sensor platform is achieved by a proposed adaptive radio transmission power control algorithm, and some straightforward methods, including adopting low power ICs and high efficient power management circuits, low duty cycle radio polling and switching off radio between two adjacent data packets' transmission. The adaptive transmission power control algorithm is based on the statistical average of the path loss estimations using a moving average filter. The algorithm is implemented in the wireless node and relies on the received signal strength feedback piggybacked in the ACK packet from the base station node to estimate the path loss. Therefore, it does not need any control packet overheads. Several experiments are carried out to investigate the link quality of radio channels, validate and evaluate the proposed adaptive transmission power control algorithm, including static and dynamic experiments.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.585-586
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• 2008

In this paper, a novel beta-multiplier reference current source circuit for the 800mV power-supply voltage is presented. In order to cope with the narrow input common-mode range of the OpAmp in the reference circuit, shunt resistive voltage divider branches were deployed. High gain OpAmp was designed to compensate intrinsic low output resistance of the MOS transistors. The proposed reference circuit was designed in a standard 0.18um CMOS process with nominal Vth of 420mV and -450mV for nMOS and pMOS transistor respectively. The total power consumption including OpAmp is less than 50uW.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.125-131
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• 2018

STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.28-36
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• 1997

In this paper, system application techniques of a low-voltage low-power CMOS comparator are proposed. The proposed techniques employ poly-layer lines instead of conventional dummy cells to improve the accuracy of comparators which are located in both ends of a comparator array. This technique is easily applicable for hihg-density systems such as memory. The proposed circuits are implemented using a 0.6 um signle-poly double-metal n-well CMOS technology and the dissipated power is 0.38 mW. at a 20MHz clock speed based on a 3V supply. The comparator offsets are measured separately and compared for system applications. Using the proposed techniues, the measured comparator offsets are reduced by 40% of a conventional case.

• Journal of Electrical Engineering and Technology
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• v.9 no.3
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• pp.812-819
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• 2014

The proposed technical work attempts to compare the two key technologies of power distribution, i.e. direct current (DC) and alternating current (AC) in a fiscal manner. The DC versus AC debate has been around since the earliest days of electric power. Here, at least four types of a low voltage DC (LVDC) distribution are examined as an alternative to the existing medium voltage AC (MVAC) distribution with an economic assessment technique for a project investment. Besides, the sensitivity analysis will be incorporated in the overall economic analysis model to cover uncertainties of the input data. A detailed feasibility study indicates that many of the common benefits claimed for an LVDC distribution will continue to grow more profoundly as it is foreseen to arise with the increased integration of renewable energy sources and the proliferation of energy storage associated with the enhanced utilization of uninterruptible power supply (UPS) systems.