• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1826-1829
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• 2005

Recent advancement in wireless communications and electronics has enabled the development of low power sensor network. Wireless sensor network are often used in remote monitoring control applications, health care, security and environmental monitoring. Wireless sensor networks are an emerging technology consisting of small, low-power, and low-cost devices that integrate limited computation, sensing, and radio communication capabilities. Sensor network platform for health care has been designed, fabricated and tested. This system consists of an embedded micro-controller, Radio Frequency (RF) transceiver, power management, I/O expansion, and serial communication (RS-232). The hardware platform uses Atmel ATmega128L 8-bit ultra low power RISC processor with 128KB flash memory as the program memory and 4KB SRAM as the data memory. The radio transceiver (Chipcon CC1000) operates in the ISM band at 433MHz or 916MHz with a maximum data rate of 76.8kbps. Also, the indoor radio range is approximately 20-30m. When many sensors have to communicate with the controller, standard communication interfaces such as Serial Peripheral Interface (SPI) or Integrated Circuit ($I^{2}C$) allow sharing a single communication bus. With its low power, the smallest and low cost design, the wireless sensor network system and wireless sensing electronics to collect health-related information of human vitality and main physiological parameters (ECG, Temperature, Perspiration, Blood Pressure and some more vitality parameters, etc.)

• 마이크로전자및패키징학회지
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• 제23권2호
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• pp.37-42
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• 2016

전력가격의 상승으로 데이터센터의 운영비 부담이 늘어나는 가운데, 슈퍼컴퓨터에 저전력 프로세서를 사용하여 데이터센터의 전력소모를 감소시키는 연구가 활발하다. 일반적으로 모바일 기기 등의 운용환경을 기준으로 신뢰성 평가가 이루어지는 저전력 프로세서를 슈퍼컴퓨터에 사용하는 경우 상대적으로 가혹한 운용환경으로 인해 물리적, 기계적 신뢰성 문제가 발생할 수 있다. 이 논문은 슈퍼컴퓨터 운용 환경을 바탕으로 저전력 프로세서 패키지의 수명을 평가하였다. 먼저 문헌조사, 고장모드 및 치명도 분석을 통해 저전력 프로세서 패키지의 주요 고장원인으로 온도 사이클을 선정하였다. 부하-온도 관계를 확인하기 위해 단계적인 부하를 가하며 프로세서의 온도를 측정하였다. 가장 보수적인 운용조건을 가정하고 온도 사이클에 관련된 고장물리 모델을 이용한 결과 저전력 프로세서 패키지의 기대수명은 약 3년 이하로 예측되었다. 실험 결과를 바탕으로 저전력 프로세서 패키지의 기대수명을 향상하는 방법을 제시하였다.

• 전자공학회논문지A
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• 제33A권5호
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• pp.212-221
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• 1996

A CMOS comparator is designed for low voltage and low power operations. The proposed comparator consists of a preadmplifier followed by a regenerative latch. The preasmplifier reduces the power consumption to a half with the power-down mode and the dynamic offsets of the latch, which is affected by each device mismatch, is statistically analyzed. The circuit is designed and simulated using a 0.8.mu.m n-well CMOS process and the dissipated power is 0.16mW at a 20MHz clock speed based on a 3V supply.

• 전자공학회지
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• 제25권5호
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• pp.31-41
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• 1998

With the advent of portable electronic systems, power consumption has recently become a major issue in circuit and system design. Furthermore, the sophisticated fabrication technology makes it possible to embed more functions and features in a VLSI chip, consequently calling for both higher performance and lower power to deal with the ever growing complexity of system algorithms than in the past. VLSI designers should cope with two conflicting constraints, high performance and low power, offering an optimum trade off of these constraints to meet requirements of system. Historically, VLSI designers have focused on performance improvement, and power dissipation was not a design criteria but an afterthought. This design paradigm should be changed, as power is emerging as the most critical design constraint. In VLSI design, low power design can be accomplished through many ways, for instance, process, circuit/logic design, architectural design, and etc.. In this paper, a few low power design examples, which have been used in 8 bit micro-controller core, and can be used also in 4/16/32 bit micro-controller cores, are presented in the areas of circuit, logic and architectural design. We first propose a low power guidelines for micro-controller design in SAMSUNG, and more detailed design examples are followed applying 4 specific design guidelines. The 1st example shows the power reduction through reduction of number of state clocks per instruction. The 2nd example realized the power reduction by applying RISC(Reduced Instruction Set Computer) concept. The 3rd example is to optimize the algorithm for ALU(Arithmetic Logic Unit) to lower the power consumption, Lastly, circuit cells designed for low power are described.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제50권10호
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• pp.501-507
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• 2001

In this paper, new high-efficiency zero voltage switching (ZVS) AC-DC boost converter is proposed to achieve power factor correction by simplifing energy recovery circuit. A lot of high power factor correction circuits have been proposed and applied to increase input power factor and efficiency. Most of these circuits may obtain unity power factor and achieve sinusoidal current waveform with zero voltage or/and zero current switching. However, it is difficult for them to obtain low cost, small size, low weight, and low noise. The topology proposed to improve these problems can compact the devices in circuit and can achieve high efficiency ZVS AC-DC boost converter. Simulation and experimental results show that this topology is capable of obtaining high power factor and increasing the efficiency of the system.

• 대한원격탐사학회:학술대회논문집
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• 대한원격탐사학회 2004년도 Proceedings of ISRS 2004
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• pp.91-94
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• 2004

Ubiquitous sensor network is to manage and collect information autonomously by communicating user around device. Security requirements in Ubiquitous based on sensor network are as follows: a location of sensor, a restriction of performance by low electric power, communication by broadcasting, etc. We propose new mutual authentication protocol using a low power of sensor node. This protocol solved a low power problem by reducing calculation overload of sensor node using two steps, RM(Register Manager) and AM(Authentication Manager). Many operations performing the sensor node itself have a big overload in low power node. Our protocol reduces the operation number from sensor node. Also it is mutual authentication protocol in Ubiquitous network, which satisfies mutual authentication, session key establishment, user and device authentication, MITM attack, confidentiality, integrity, and is safe the security enemy with solving low electric power problem.

• ETRI Journal
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• 제30권3호
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• pp.451-460
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• 2008

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low-power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low-power commutators based on an advanced interconnection, and parallel-pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel-pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.

• 융합보안논문지
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• 제12권3호
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• pp.27-34
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• 2012

본 논문에서는 IEEE와 ZigBee Alliance에서 제정한 국제 표준안과 호환성을 가지고, 저전력 저비용을 강점으로 하는 지그비를 이용하여 상대적으로 열악한 전송 환경을 갖지만 적용이 용이한 무선망과, 기존 무선 기반 센서 네트워크 단점을 극복하기 위해 이미 구축되어 있는 동축케이블을 이용한 유선망을 연동함에 있어서 RSSI 모니터링을 통한 출력파워 조절 알고리즘을 이용하여 저전력 소모를 특징으로 하는 지그비 장치의 새로운 저전력 소모 방안을 제시하였다. 보다 최적화된 저전력 소모를 가능하도록 실험을 통해 RSSI 모니터링을 통한 출력 파워 조절 알고리즘의 유효성을 검증하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 C
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• pp.1437-1439
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• 1999

This paper describes test method though low voltage power system implementation for high impedance fault relay test before its operation in real power system. Through this test, relay tested its function and algorithm. In this paper, we will provides test method using low voltage power system and its results.

• Journal of information and communication convergence engineering
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• 제5권1호
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• pp.59-63
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• 2007

In this paper, a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.