• Title/Summary/Keyword: Low delay

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Identification of a likely pathogenic variant of YY1 in a patient with developmental delay

  • Bae, Soyoung;Yang, Aram;Ahn, Ja-Hye;Kim, Jinsup;Park, Hyun Kyung
    • Journal of Genetic Medicine
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    • v.18 no.1
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    • pp.60-63
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    • 2021
  • Gabriel-de Vries syndrome, caused by the mutation of YY1, is a newly defined genetic syndrome characterized by developmental delay, facial dysmorphism, and intrauterine growth retardation. A 7-month-old girl presented developmental delay and subtle facial dysmorphism including facial asymmetry, micrognathia, and low-set ears. Whole exome sequencing identified a de novo heterozygous missense variant in the YY1 (c.1220A>G; p.His407Arg) gene. Here, we examined the clinical and genetic characteristics of an infant with a novel likely pathogenic variant of YY1. This case expands the phenotypic spectrum of Gabriel-de Vries syndrome.

Implementation of a High Performance XOR-XNOR Circuit

  • Kim, Jeong-Beom
    • The Journal of the Korea institute of electronic communication sciences
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    • v.17 no.2
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    • pp.351-356
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    • 2022
  • The parity function can be implemented with XOR (exclusive-OR) and XNOR (exclusive NOR) circuit. In this paper we propose a high performance XOR-XNOR circuit. The proposed circuitreduced the internal load capacitance on critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit presents the improved characteristics in average propagation delay time, power dissipation, power-delay product (PDP), and energy-delay-product (EDP). The proposed circuits are implemented with standard CMOS 0.18um technology. Computer simulations using SPICE show that the proposed circuit realizes the expected logic functions and achieves a reasonable performance.

Task Scheduling and Resource Management Strategy for Edge Cloud Computing Using Improved Genetic Algorithm

  • Xiuye Yin;Liyong Chen
    • Journal of Information Processing Systems
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    • v.19 no.4
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    • pp.450-464
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    • 2023
  • To address the problems of large system overhead and low timeliness when dealing with task scheduling in mobile edge cloud computing, a task scheduling and resource management strategy for edge cloud computing based on an improved genetic algorithm was proposed. First, a user task scheduling system model based on edge cloud computing was constructed using the Shannon theorem, including calculation, communication, and network models. In addition, a multi-objective optimization model, including delay and energy consumption, was constructed to minimize the sum of two weights. Finally, the selection, crossover, and mutation operations of the genetic algorithm were improved using the best reservation selection algorithm and normal distribution crossover operator. Furthermore, an improved legacy algorithm was selected to deal with the multi-objective problem and acquire the optimal solution, that is, the best computing task scheduling scheme. The experimental analysis of the proposed strategy based on the MATLAB simulation platform shows that its energy loss does not exceed 50 J, and the time delay is 23.2 ms, which are better than those of other comparison strategies.

A Simple CPW-Fed UWB Antenna Design

  • Park, Sang-Yong;Oh, Seon-Jeong;Park, Jong-Kweon
    • Journal of electromagnetic engineering and science
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    • v.10 no.1
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    • pp.13-17
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    • 2010
  • In this paper, we have described a simple CPW-fed UWB antenna for wireless UWB communication. The proposed antenna consists of two symmetrical strips having two steps and CPW feeding. Two techniques(symmetrical structure, two steps) are used to produce good low-dispersion and impedance matching. The proposed UWB antenna has an omni directional radiation pattern, compact size, low dispersion, and low cost.

Multicast address allocation for IPv6 (IPv6에서 멀티캐스트 어드레스 할당방법)

  • 최성미;김상언;홍경표
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.118-121
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    • 1999
  • Multicast addresses cannot be permanently assigned to particular application or group combination, but need to be available for re-use. So, this requires a dynamic multicast address allocation and release mechanism. For a dynamic multicast address allocation and release mechanism, we must consider low blocking probability, low delay, low control traffic overhead. In this paper, we suggest a efficient dynamic multicast address allocation and release mechanism based on the multicast scope

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The Low-Latency Search for Gravitational Waves from Compact Binary Coalescence

  • Oh, Sang-Hoon
    • The Bulletin of The Korean Astronomical Society
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    • v.36 no.1
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    • pp.70.1-70.1
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    • 2011
  • During the summer of 2010, the first low-latency search for gravitational waves from compact binary coalescences was performed using the LIGO and Virgo instruments. The aim was to provide triggers for follow-up by electromagnetic telescopes. In this presentation we will describe the low-latency pipeline used to produce these triggers, including the time-delay-based procedure used to localize them on the sky.

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Distortion Variation Minimization in low-bit-rate Video Communication

  • Park, Sang-Hyun
    • Journal of information and communication convergence engineering
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    • v.5 no.1
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    • pp.54-58
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    • 2007
  • A real-time frame-layer rate control algorithm with a token bucket traffic shaper is proposed for distortion variation minimization. The proposed rate control method uses a non-iterative optimization method for low computational complexity, and performs bit allocation at the frame level to minimize the average distortion over an entire sequence as well as variations in distortion between frames. The proposed algorithm does not produce time delay from encoding, and is suitable for real-time low-complexity video encoder. Experimental results indicate that the proposed control method provides better visual and PSNR performances than the existing rate control method.

Analysis and Design of High Efficiency Feedforward Amplifier Using Distributed Element Negative Group Delay Circuit (분산 소자 형태의 마이너스 군지연 회로를 이용한 고효율 피드포워드 증폭기의 분석 및 설계)

  • Choi, Heung-Jae;Kim, Young-Gyu;Shim, Sung-Un;Jeong, Yong-Chae;Kim, Chul-Dong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.6
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    • pp.681-689
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    • 2010
  • We will demonstrate a novel topology for the feedforward amplifier. This amplifier does not use a delay element thus providing an efficiency enhancement and a size reduction by employing a distributed element negative group delay circuit. The insertion loss of the delay element in the conventional feedforward amplifier seriously degrades the efficiency. Usually, a high power co-axial cable or a delay line filter is utilized for a low loss, but the insertion loss, cost and size of the delay element still acts as a bottleneck. The proposed negative group delay circuit removes the necessity of the delay element required for a broadband signal suppression loop. With the fabricated 2-stage distributed element negative group delay circuit with -9 ns of total group delay, a 0.2 dB of insertion loss, and a 30 MHz of bandwidth for a wideband code division multiple access downlink band, the feedforward amplifier with the proposed topology experimentally achieved a 19.4 % power added efficiency and a -53.2 dBc adjacent channel leakage ratio with a 44 dBm average output power.

Non-Reference P Frame Coding for Low-Delay Encoding in Internet Video Coding (IVC의 저지연 부호화 모드를 위한 비참조 P 프레임의 부호화 기법)

  • Kim, Dong-Hyun;Kim, Jin-Soo;Kim, Jae-Gon
    • Journal of Broadcast Engineering
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    • v.19 no.2
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    • pp.250-256
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    • 2014
  • Non-reference P frame coding is used to enhance coding efficiency in low-delay encoding configuration of Internet Video Coding (IVC), which is being standardized as a royalty-free video codec in MPEG. The existing method of non-reference P frame coding which was adopted in the reference Test Model of IVC (ITM) 4.0 adaptively applies a non-reference P frame with a fixed coding structure based on the magnitude of motion vectors (MVs), however, which unexpectedly degrades the coding efficiency for some sequences. In this paper, the existing non-reference P frame coding is improved by changing non-reference P frame coding structure and applying a new adaptive method using the ratio of the amount of generated bits of non-reference frames to that of reference frames as well as MVs. Experimental results show that the proposed non-reference P frame coding gives 6.6% BD-rate bit saving in average over ITM 7.0.

Design and FPGA Implementation of FBMC Transmitter by using Clock Gating Technique based QAM, Inverse FFT and Filter Bank for Low Power and High Speed Applications

  • Sivakumar, M.;Omkumar, S.
    • Journal of Electrical Engineering and Technology
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    • v.13 no.6
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    • pp.2479-2484
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    • 2018
  • The filter bank multicarrier modulation (FBMC) technique is one of multicarrier modulation technique (MCM), which is mainly used to improve channel capacity of cognitive radio (CR) network and frequency spectrum access technique. The existing FBMC System contains serial to parallel converter, normal QAM modulation, Radix2 inverse FFT, parallel to serial converter and poly phase filter. It needs high area, delay and power consumption. To further reduce the area, delay and power of FBMC structure, a new clock gating technique is applied in the QAM modulation, radix2 multipath delay commutator (R2MDC) based inverse FFT and unified addition and subtraction (UAS) based FIR filter with parallel asynchronous self time adder (PASTA). The clock gating technique is mainly used to reduce the unwanted clock switching activity. The clock gating is nothing but clock signal of flip-flops is controlled by gate (i.e.) AND gate. Hence speed is high and power consumption is low. The comparison between existing QAM and proposed QAM with clock gating technique is carried out to analyze the results. Conversely, the proposed inverse R2MDC FFT with clock gating technique is compared with the existing radix2 inverse FFT. Also the comparison between existing poly phase filter and proposed UAS based FIR filter with PASTA adder is carried out to analyze the performance, area and power consumption individually. The proposed FBMC with clock gating technique offers low power and high speed than the existing FBMC structures.