• Journal of Korea Society of Digital Industry and Information Management
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• 제18권1호
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.561-564
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• 2005

In this paper, we present a new JPEG (Joint Photograph Experts Group) compression architecture which compresses still image into fixed size of bitstream to use restricted system memory efficiently. The size of bitstream is determined by the complexity of image and the quantization table. But the quantization table is set in advance the complexity of image is the essential factor. Therefore the size of bitstream for high complexity image is large and the size for low complexity image is small. This means that the management of restricted system memory is difficult. The proposed JPEG encoder estimates the size of bitstream using the correlation between consecutive frames and selects the quantization table suited to the complexity of image. This makes efficient use of system memory.

• Journal of Korea Multimedia Society
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• 제10권12호
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• pp.1551-1558
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• 2007

The standard of evaluating function of speech coder for mobile telecommunication can be shown in channel capacity, noise immunity, encryption, complexity and encoding delay largely. This study is an algorithm to reduce complexity applying to CDMA(Code Division Multiple Access) mobile telecommunication system, which has a benefit of keeping the existing advantage of telecommunication quality and low transmission rate. This paper has an objective to reduce the computing complexity by controlling the frequency band nonuniform during the changing process of LSP(Line Spectrum Pairs) parameters from LPC(Line Predictive Coding) coefficients used for EVRC(Enhanced Variable-Rate Coder, IS-127) speech coders. Its experimental result showed that when comparing the speech coder applied by the proposed algorithm with the existing EVRC speech coder, it's decreased by 45% at average. Also, the values of LSP parameters, Synthetic speech signal and Spectrogram test result were obtained same as the existing method.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅳ
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• pp.2232-2235
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• 2003

In speech communication systems where two different speech codecs are interoperated, transcoding algorithm is a good approach because of its low complexity and improved synthesized speech quality. This paper proposes an efficient method to further improve the performance of transcoding algorithms as well as to reduce the complexity. In the conventional transcoding algorithms. a post-filter and a perceptual weighting filter should be operated sequentially because both decoding and encoding processes are needed. This results in the redundancy of the processing in terms of complexity and perceptual quality. Using the fact that their filter structures are similar, we replaced the two filters with one. The proposed algorithm requires 72.8% lower complexity than the conventional transcoding algorithm when we compare only the complexity of the filtering processes. The results of both objective and subjective tests verify that the proposed algorithm has slightly better quality than the conventional one.

• Journal of the Korean Operations Research and Management Science Society
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• 제17권2호
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• pp.45-54
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• 1992

It become increasingly important to design user interface to carry low complexity. The cognitive limitations of users severely restrict utility of highly intelligent but complex modern systems. Since humans are known to use schemas to reduce cognitive complexity, imposing good consistency to an interface design that may help that user form useful schemas will provide powerful control over the complexity. This present a research effort to develop a quantitative method for evaluating interface complexity that the user would experience planning his or her course of action. Taking into account the user's potential schemas, a quantitative measure based on information theory was develped to assess the navigational complexity. This approach does not rely on the subjective judgment of the researcher as most schemes dealing with user schemas do. The proposed method may benefit the rapid prototyping approach to design a better user interface by allowing handy assessment of the design.

• Journal of the Institute of Electronics Engineers of Korea SP
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• 제47권3호
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• pp.87-95
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• 2010

Portable multi-media products which can service the highest audio-quality by using lossless audio codec has been released and the international lossless codecs, MPEG-4 audio lossless coding(ALS) and MPEG-4 scalable lossless coding(SLS), were standardized by MPEG in 2006. The simple profile of MPEG-4 ALS, it supports up to stereo, was defined by MPEG in 2009. The lossless audio codec should have low-complexity in stereo to be widely used in portable multi-media products. But the previous researches of MPEG-4 ALS have focused on an improvement of compression ratio, a complexity reduction in multi-channels coding, and a selection of linear prediction coefficients(LPCs) order. In this paper, the complexity and compression ratio of MPEG-4 ALS encoder is analyzed in simple profile of MPEG-4 ALS, the method to reduce a complexity of MPEG-4 ALS encoder is proposed. Based on an analysis of complexity of MPEG-4 ALS encoder, the complexity of short-term prediction filter of MPEG-4 ALS encoder is reduced by using the low-complexity filter that is proposed in previous research to reduce the complexity of MPEG-4 ALS decoder. Also, we propose a joint coding decision method, it reduces the complexity and keeps the compression ratio of MPEG-4 ALS encoder. In proposed method, the operation of joint coding is decided based on the relation between cross-correlation of residual and compression ratio of joint coding. The performance of MPEG-4 ALS encoder that has the method and low-complexity filter is evaluated by using the MPEG-4 ALS conformance test file and normal music files. The complexity of MPEG-4 ALS encoder is reduced by about 24% by comparing with MPEG-4 ALS reference encoder, while the compression ratio by the proposed method is comparable to MPEG-4 ALS reference encoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제34권5C호
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• pp.498-504
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• 2009

A high-performance low-complexity decoding algorithm for LDPC codes is proposed in this paper, which has the advantages of both bit-flipping (BF) algorithm and sum-product algorithm (SPA). The proposed soft bit-flipping algorithm requires only simple comparison and addition operations for computing the messages between bit and check nodes, and the amount of those operations is also small. By increasing the utilization ratio of the computed messages and by adopting nonuniform quantization, the signal-to-noise ratio (SNR) gap to the SPA is reduced to 0.4dB at the frame error rate of 10-4 with only 5-bit assignment for quantization. LDPC codes with high column or row weights, which are not suitable for the SPA decoding due to the complexity, can be practically implemented without much worsening the error performance.

• Journal of the Institute of Electronics Engineers of Korea CI
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• 제40권6호
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• pp.118-126
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• 2003

This paper presents a low-complexity algorithm lot browsing a HD bit stream in DTV PVR according to its characteristics and also presents its implementation results. We propose an efficient algorithm which detects shots using some information after decoding MPEG-2 data, clusters them into scene and episode, and intelligently browses them according to some criteria after calculating their complexity. Some simulation results are presented to show the performance feasibility of the proposed algorithm. To implement it in real time, we propose an efficient hybrid architecture which partitions the algorithm into two parts of hardware and software. The hardware covers decoding process and extraction of some basic information which take most complexity in implementing the algorithm. The software covers the heuristic part of tile algorithm which has low complexity and needs to be expandable.

• ETRI Journal
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• 제39권3호
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• pp.326-335
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• 2017

In the uplink transmission of massive (or large-scale) multi-input multi-output (MIMO) systems, large dimensional signal detection and its hardware design are challenging issues owing to the high computational complexity. In this paper, we propose low-complexity hardware architectures of Richardson iterative method-based massive MIMO detectors. We present two types of massive MIMO detectors, directly mapped (type1) and reformulated (type2) Richardson iterative methods. In the proposed Richardson method (type2), the matrix-by-matrix multiplications are reformulated to matrix-vector multiplications, thus reducing the computational complexity from $O(U^2)$ to O(U). Both massive MIMO detectors are implemented using a 65 nm CMOS process and compared in terms of detection performance under different channel conditions (high-mobility and flat fading channels). The hardware implementation results confirm that the proposed type1 Richardson method-based detector demonstrates up to 50% power savings over the proposed type2 detector under a flat fading channel. The type2 detector indicates a 37% power savings compared to the type1 under a high-mobility channel.

• ETRI Journal
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• 제32권4호
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• pp.588-595
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• 2010

This paper proposes encoding and decoding for nonlinear product codes and investigates the performance of nonlinear product codes. The proposed nonlinear product codes are constructed as N-dimensional product codes where the constituent codes are nonlinear binary codes derived from the linear codes over higher order alphabets, for example, Preparata or Kerdock codes. The performance and the complexity of the proposed construction are evaluated using the well-known nonlinear Nordstrom-Robinson code, which is presented in the generalized array code format with a low complexity trellis. The proposed construction shows the additional coding gain, reduced error floor, and lower implementation complexity. The (64, 24, 12) nonlinear binary product code has an effective gain of about 2.5 dB and 1 dB gain at a BER of $10^{-6}$ when compared to the (64, 15, 16) linear product code and the (64, 24, 10) linear product code, respectively. The (256, 64, 36) nonlinear binary product code composed of two Nordstrom-Robinson codes has an effective gain of about 0.7 dB at a BER of $10^{-5}$ when compared to the (256, 64, 25) linear product code composed of two (16, 8, 5) quasi-cyclic codes.