• Transactions on Electrical and Electronic Materials
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• 제5권1호
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• pp.19-23
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• 2004

A novel method of high speed, accurate circuit simulation in 3-dimensional (3-D) parallel-plate capacitors is investigated. The basic concept of the circuit simulation methods is partial element equivalent circuit model. The three test structures of 3-D parallel-plate capacitors are fabricated by using multi-layer low-temperature co-fired ceramic (LTCC) process and their S-parameters are measured between 50 MHz and 5 GHz. S-parameters are converted to Y-parameters, for comparing measured data with simulated data. The circuit model parameters of the each building block are optimized and extracted using HSPICE circuit simulator. This method is convenient and accurate so that circuit design applications can be easily manipulated.

• KIEE International Transactions on Electrophysics and Applications
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• 제4C권6호
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• pp.288-294
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• 2004

In this paper, a ceramic antenna and diplexer are designed for dual-band handset ap plications. Basically, the antenna is designed by using the meander line configuration. The diplexer presented in this paper is composed of both low- and high-pass filters. We have designed the low- and high-pass filters with attenuation poles to improve the attenuation performances of the diplexer. The attenuation poles are located at each rejection frequency region so as to improve the shrinkage characteristic of the diplexer. In order to accomplish the volume effectiveness, the antenna and the diplexer have been designed and fabricated in a multi-layer structure. The diplexer designed with a multi-layer structure has inductors and capacitors, which are implemented by LTCC (Low Temperature Co-fired Ceramics) process technique. Design of the multi-layer antenna and diplexer has been achieved by employing the full 3-D EM simulation. The designed antenna and diplexer offer excellent return loss and broadband performances with highly isolated rejection performance.

• 한국전자파학회논문지
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• 제20권4호
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• pp.323-332
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• 2009

본 논문에서는 기존의 $\lambda_0$/4 단락 스터브 대역 통과 필터의 특성을 개선하여 LTCC(Low Temperature Co-fired Ceramic)을 이용하여 UWB(Ultra Wideband) 응용에 적합한 필터 기술을 소개한다. 높은 유전 상수의 기판($\varepsilon_r$ = 40)상에 기존의$\lambda_0$/4의 단락 스터브 대역 통과 필터 기술을 적용하기 위하여 기존의 필터와는 다르게 낮은 특성 임피던스 선로를 이용하여 결과적으로 스터브의 수를 다섯 개에서 두 개로 감소시켰다. 또한, 3개의 단락 결합 선로를 이용해서 5.15 GHz에서 5.825 GHz의 주파수 범위에서 WLAN(Wireless Local Area Network) 저지 대역을 특성 내에 삽입하였다. 본 필터는 통과 대역에서 1 dB 미만의 삽입 손실과 10 dB 이상의 반사 손실을 갖는 것으로 측정되었고, 109.49 %의 대역폭 율이 달성되었다. 측정 결과는 시뮬레이션 결과와 잘 일치한다. 필터의 크기는 $4{\times}8{\times}0.57\;mm^3$이다.

• 한국전기전자재료학회논문지
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• 제30권11호
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• pp.683-687
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• 2017

We investigated the structure of an ultra-thin insulating board with low thermal conductivity along z-axis, which was based on the idea of void layers created during the glass infiltration process for the zero-shrinkage low-temperature co-fired ceramic (LTCC) technology. An alumina and four glass powders were chosen and prepared as green sheets by the tape casting method. After comparison of the four glass powders, bismuth glass was selected for the experiment. Since there is no notable reactivity between alumina and bismuth glass, alumina was selected as the supporting additive in glass layers. With 2.5 vol% of alumina powder, glass green sheets were prepared and stacked alternately with alumina green sheet to form the 'alumina/glass (including alumina additive)/alumina' structure. The stacked green sheets were sintered into an insulating substrate. Scanning electron microscopy revealed that the additive alumina formed supporting bridges in void layers. The depth and number of the stacking layers were varied to examine the insulating property. The lowest thermal conductivity obtained was 0.23 W/mK with a $500-{\mu}m-thick$ substrate.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.81-82
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• 2007

This paper presents a WLAN band active monopole antenna which is made of a CPW-fed monopole antenna and a low noise amplifier implemented on single-layer low-temperature co-fired ceramic (LTCC) substrate. Planar active antenna measure return loss and power test. (drain voltage = 4V, gate voltage = -0.6V). The bandwidth, is 540MHz, return loss is -38dB.

• Journal of electromagnetic engineering and science
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• 제10권1호
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• pp.28-34
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• 2010

This paper introduces a new U.S. ultra-wideband(UWB: 3.1~10.6 GHz) 1:2 power divider based on a single section Wilkinson type configuration. The divider provides very flat in-band power splitting, high isolation, low insertion loss, sharp roll-off bandpass filtering, and DC blocking characteristics. The circuit consists of a $\lambda$/4 Y resonator, three capacitively coupled $\lambda$/2 short-circuited lines, and a resistor between the two output ports. The circuit structure was simulated with ADS and HFSS, and realized with low-temperature co-fired ceramic(LTCC) green tape, which has a dielectric constant of 7.8. $|S_{11}|$ better than 10 dB, $|S_{21}|$ and $|S_{31}|$ less than 3.2 dB, with both $|S_{22}|$ and $|S_{32}|$ measured as better than 12 dB for the whole UWB band. Measurement results agree closely with HFSS simulation results. The power divider has a compact size of $4\times9\times0.6mm^3$.

• ETRI Journal
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• 제31권3호
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• pp.254-262
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• 2009

This paper presents a novel simple filter design method based on a parallel short-ended coupled-line structure with capacitive loading for size reduction and ultra-broad rejection of spurious passbands. In addition, the introduction of a cross-coupling capacitor into the miniaturized coupled-line can create a transmission zero at the second harmonic frequency for better frequency selectivity and attenuation level. The aperture compensation technique is also applied to achieve a strong coupling in the coupled-line section. The influence of using the connecting transmission line to cascade two identical one-stage filters is studied for the first time. Specifically, such a two-stage bandpass filter operating at 2.3 GHz with a fractional bandwidth of 10% was designed and realized with low-temperature co-fired ceramic technology for application in base stations that need high power handling capability. It achieved attenuation in excess of -40 dB up to $4f_0$ and low insertion loss of -1.2 dB with the size of 10 mm ${\times}$ 7 mm ${\times}$ 2.2 mm. The measured and simulated results showed good agreement.

• 한국전자파학회논문지
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• 제20권8호
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• pp.730-738
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• 2009

본 논문에서는 선행 연구된 LTCC(Low Temperature Co-fired Ceramic) 적층형 대역 통과 필터 구조에 대해 기생 성분을 고려한 등가회로를 제시하고 SOC(Short-Open Calibration) 기법을 적용하여 소자값을 추출하는 과정을 보인다. 추출된 소자 값을 제시한 등가회로에 적용함으로써 위성 DMB에 적용 가능한 2차 LTCC 필터를 설계 제작하였다. 비유전율 7.8의 Dupont951을 사용하여 제작된 필터의 크기는 $2.4{\times}3.8{\times}0.378mm^3$이다. 측정 결과 1.4 dB의 삽입 손실과 32.3 dB의 반사 손실을 보였으며 설계 사양과 대체로 일치함을 보인다.

• 한국세라믹학회지
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• 제38권7호
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• pp.597-601
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• 2001

The effect of CuO, $B_2$ $O_3$, $V_2$ $O_{5}$ and CuO-B $i_2$ $O_3$additives on microwave dielectric properties of (P $b_{0.45}$C $a_{0.55}$) [(F $e_{0.5}$N $b_{0.5}$)$_{0.9}$S $n_{0.1}$] $O_3$(PCFNS) were investigated. The PCFNS ceramics were sintered at 11$65^{\circ}C$. To decrease the sintering temperature for using as a low-temperature co-firing ceramics (LTCC), CuO, $B_2$ $O_3$, $V_2$ $O_{5}$ and CuO-B $i_2$ $O_3$were added to the PCFNS. As the content of CuO increased, the sintered density and dielectric constant increased and the temperature coefficient of resonance frequency ($\tau$$_{f}$) shifted to the positive value. When the CuO-B $i_2$ $O_3$were added, dielectric properties were $\varepsilon$$_{r}$ of 83, Q. $f_{0}$ of 6085 GHz, and $\tau$$_{f}$ of 8ppm/$^{\circ}C$ at a sintering temperature of 100$0^{\circ}C$. The relationship between the microstructure and properties of ceramics was studied by X-ray diffraction and scanning electron microscopy.icroscopy.y.icroscopy.y.

• 마이크로전자및패키징학회지
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• 제12권2호
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• pp.105-109
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• 2005

본 논문은 LTCC 공정에 기반을 둔 GSM/DCS dual band 의 소형화된 antenna switch module을 공정변수 따른 특성의 왜곡을 안정화시키는 연구를 수행하였다. 특히 tape thickness의 변화에 따라 패턴간의 기생 커플링이 주된 변수로 작용한다. 두께 50um인 tape으로 제작된 시편의 사이즈는 $4.5{\times}3.2{\times}0.8 mm^3$이고 insertion loss는 Rx mode와 Tx mode 각각 ldB. 1.2dB 이하이다. 공정상에서 tape thickness의 변화에 따라 개발된 모듈의 특성 안정성을 검증하기 위해 각 블록-다이플렉서,필터, 바이어스 회로-을 probing method을 이용, 측정하였고, 각 블록간의 상호관계는 VSWR을 계산하여 비교하였다. 또한 회로적 관점에서 특성 개선을 위해 바이어스 회로부분의 집중소자형과 분포소자형을 구현하여 서로 비교 분석하였다. 이를 통해 각 블록의 측정과 계산된 VSWR의 데이터는 공정변수에 의해 변화된 전체 module의 특성과 안정성 거동을 파악하는데 좋은 정보를 준다. Tape thickness변화에도 불구하고 다이플렉스의 matching값은 연결되는 바이어스 회로와 LPF의 matching값과 상대 matching이 되면서, 낮은 VSWR을 유지하여 전체 insertion loss가 안정화되는 것을 확인하였다. 더불어 분포소자형 바이어스 회로보다는 집중소자형이 다른 회로블럭과의 관계에서 더 좋은 매칭을 이루어 loss개선에 일조하였다. Tape thickness가 6 um이상의 변화를 가져와도 집중소자형 바이어스 회로는 낮은 손실을 유지하여 더 넓은 안정 범위를 가져오기 때문에 양산에 적합한 구조가 될 수 있다 그리고, probing method에 의한 안정성 특성 추출은 세라믹에 임베디드된 수동회로들의 개발에 충분히 적용될 수 있다.