• Journal of Information Processing Systems
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• v.10 no.3
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• pp.412-428
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• 2014

Request oriented sensor networks have stricter requirements than conventional event-driven or periodic report models. Therefore, in this paper we propose a minimum energy data aggregation (MEDA), which meets the requirements for request oriented sensor networks by exploiting a low power real-time scheduler, on-demand time synchronization, variable response frame structure, and adaptive retransmission. In addition we introduce a test bed consisting of a number of MEDA prototypes, which support near real-time bidirectional sensor networks. The experimental results also demonstrate that the MEDA guarantees deterministic aggregation time, enables minimum energy operation, and provides a reliable data aggregation service.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.282-285
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• 2002

In this paper, we designed of low power system by using dynamic scaling. As an effective low-power design, dynamic voltage/frequency scaling recently has received a lot of attention. In dynamic frequency scheme, all execution cycles are driven by the clock frequency that switched frequency dynamically at run time. The algorithm schedules lower frequency operators at earlier steps and higher frequency operators to later steps. This algorithm assigned the frequency for each execution cycle then it adjusted the voltage associated with the frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.35-38
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• 2018

This paper describes a low-power MPPT interface for DC-type energy harvesting sources. The proposed circuit consists of an MPPT controller, a bias generator, and a voltage detector. The MPPT controller consists of an MPG (MPPT Pulse Generator) with a schmitt trigger, a logic gate operating according to energy type (light, heat), and a sample/hold circuit. The bias generator is designed by employing a beta multiplier structure, and the voltage detector is implemented using a bulk-driven comparator and a two-stage buffer. The proposed circuit is designed with $0.35{\mu}m$ CMOS process. The simulation results show that the designed circuit consumes less than 100nA of current at an input voltage of less than 3V and the maximum power efficiency is 99.7%. The chip area of the designed circuit is $1151{\mu}m{\times}940{\mu}m$.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.11
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• pp.1634-1640
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• 2012

This paper develops the high-efficiency drive system of the small-size electric vehicles (EVs) driven by the brushed dc motors. A power circuit for driving the dc motor is designed with the H-bridge circuit and buck converter by considering both the efficiency and cost. In order to change smoothly the rotating direction of dc motor driven by the proposed power circuit, an operating sequence for both the field current and the armature voltage according to an accelerator pedal angle is suggested. Through the simulation studies and experimental results with the low-cost 8-bit AVR, the performances of the proposed methods are verified.

• Journal of Sensor Science and Technology
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• v.21 no.3
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• pp.172-179
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• 2012

This paper presents the design and analysis of a vibration-driven electromagnetic energy harvester that uses a multi-pole magnet. The physical backgrounds of the vibration electromagnetic energy harvester are reported, and an ANSYS finite element analysis simulation has been used to determine the different alignments of the magnetic pole array with their flux lines and density. The basic working principles for a single and multi-pole magnet are illustrated and the proposed harvester has been presented in a schematic diagram. Mechanical parameters such as input frequency, maximum displacement, number of coil turns, and load resistance have been analyzed to obtain an optimized output power for the harvester through theoretical study. The paper reports a maximum of 1.005 mW of power with a load resistance of $1.9k{\Omega}$ for 5 magnets with 450 coil turns.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.30 no.1
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• pp.79-86
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• 2016

In this paper, we propose a current-driven synchronous rectifier driver circuit for LLC resonant half-bridge converters. The proposed driver circuit detects a relatively low current in the primary side of the transformer although a large current is flowing in the secondary side. Due to this feature, the driver circuit has a simple circuit structure and stabilizes the switching operation with a logic-level switching voltages for the synchronous rectifier. The operation and performance of the proposed driver circuit are confirmed with a prototype of 1kW class LLC resonant half-bridge converter. The experimental results proved that the proposed synchronous rectifier driver method improves the power conversion efficiency by around 1% and reduces the internal power loss by 17W.

• Journal of Power Electronics
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• v.10 no.6
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• pp.709-716
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• 2010

MDPS (motor driven power steering) systems have been widely used in vehicles due to their improved fuel efficiency and steering performance when compared to conventional hydraulic steering. However, the reduction of torque ripples and material cost are important issues. A low resolution position sensor for MDPS is one of the candidates for reducing the material costs. However, it may increases the torque ripple due to the current harmonics caused by low resolution encoder signals. In this paper, the torque ripple caused by the quantized rotor position of the low resolution encoder is analyzed. To reduce the torque ripples caused by the quantization of the encoder signals, the rotor position and the speed are estimated by measuring the frequency of the encoder signals. In addition, the compensating q-axis current is added to the current command so that the 6th order torque harmonic is attenuated. The reduction of torque ripples by applying the estimated rotor position and the compensated q-axis current is verified through experimental results.

• Journal of Korea Multimedia Society
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• v.8 no.2
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• pp.201-210
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• 2005

This paper proposes a power efficient 2-dimensional DCT/IDCT architecture driven by input data to be processed. The architecture achieves low power by taking advantage of the typically large fraction of zero and small-valued input processing data in video and image data compression. In particular, it skips multiplication by zero and dynamically activates/deactivates required bit-slices of fine-grain bit partitioned adders within multipliers and accumulators using simple input ANDing and bit-slice MASKing. The processed results from 1-D DCT/IDCT do not have unnecessary sign extension bits (SEBs), which are used for further power reduction in matrix transposer. The results extracted by bit-level transition activity simulations indicate significant power reduction compared to conventional designs.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.1973-1976
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• 1998

Recently, new trend in telecommunication device is to apply low voltage, about 3.3V-1.5V. However, it is undesirable in view of high efficiency and power desity which is the most important requirement in the distributed power system. Rectification loss in the output stage, in on-board converter for distributed power system are constrained to obtain high efficience at low output voltage power suppies. This paper explains the basic operational principles of three kinds of ZVS DC/DC converters with self-driven synchronous rectifier. The three topologies are analyzed by simulation and exprimentation, and the characteristics comparisons of high efficience converter are carried out in view of the minimized rectification losses in the out stage.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.1030-1035
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• 1998

This paper describes a new dc-ac inverter system, which for achieving sinusoidal ac waveform make use of parallel loaded frequency resonant inverter consisting of full bridge. Each one of the pair of switches in the inverter is driven to synchronous output frequency and the other is driven to PWM signal with resonant frequency proportional to magnitude of sine wave. Since current through switches is always zero at its turn-on in proposed inverter, low stress and low switching loss is achieved. The theoretical analysis is proved through the experimental test.