• Journal of the Korean Society for Heat Treatment
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• v.13 no.4
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• pp.259-264
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• 2000

In this study, we quantitatively measure the ion ranges of arsenic with energies ranging from 10 KeV to 100 KeV, implanted at $3^{\circ}$, $9^{\circ}$ $15^{\circ}$ the (100) plane, and the damage created during ion implantation. To obtain detailed information of ion range and damage distributions in low energy region where elastic collisions dominate the slowing down process, molecular dynamics computer simulation was performed and compared to the existing results. The effects of implant energy and degree on damage generation are present. The number of vacancy were calculated from the deposited energy using Kinchin-Pease equation. In the energy range 10 keV-100 keV, simulations show that the number of Frenckel pairs produced by As-ion bimbardment is 9 and incident angle dependence of the vacancy was the same but defects were distributed at different depth.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.83-83
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• 1999

본 연구에서는 Auger Elecrtron Spectroscopy (AES) 장비를 이용하여 Silicone Wafer 표면에 BF 이온을 주입시킨 후 Dopping 농도 및 Implantation 에너지에 따른 Si KLL Peak의 변화를 관찰하였다. 또한 PVD Ti 계열 화학물의 시료에 대하여 Peak의 Shape 변화를 관찰하였다. 1)Dopping 농도 및 Implantation 에너지에 따른 Si KLL Peak의 변화 관찰 일반적으로 Silicone 기판에 Arsenic(3가)을 Dopping 하였을 경우, Si KLL Peak의 Kinetic Energy 값은 순수 Si Peak보다 더 작은 값으로 Shift 하며, Boron (5가)을 Dopping하였을 경우에는 더 큰 값으로 Shift 한다. 이론적으로 N-type Si의 에너지 차이는 약 1.0eV로 보고되어 있으며, AES를 이용하여 실험적으로 측정된 값은 약 0.6eV정도로 알려져 있다. 이러한 차이는 Dopping 농도에 따라 Valance Band의 에너지 값이 변화하기 때문이라고 알려져 있다. 본 연구에서는 BF2를 Si에 이온 주입하여 입사 에너지 및 dose 량에 따른 Si KLL Peak의 변화를 관찰하였다. 그림1과 같이 Si KLL Peak는 Implantation Energy가 작을수록 Kinetic Energy가 높은 곳으로 Shift 한다. 이는 LOw Energy로 이온 주입하면, Projected Range (Rp)가 High Energy로 이온 주입할 때보다 작기 때문이며, 이 결과를 Secondary Ion Mass Spectroscopy (SIMS) 및 TRIM simulation을 이용하여 확인하였다. 또한 표면에서의 전자 Density의 변화와 Implantation energy와의 관계를 시료의 표면에서 반사되어 나오는 전자의 에너지 손실(Reflected Electron Energy Loss Spectroscopy:REELS)을 통하여 고찰하였다. 2) PVD Ti 계열화합물의 시료에 대한 peak의 shape 가 변화하며, TiL3M23V (Ti2) 및 TiL3M23M23 (Til) Peak의 Intensity Ratio가 변화한다. 따라서 본 연구에서는 그림 2와 같이 Ti 결합 화합물에서의 Ti Auger Peak의 특성 에너지 값과 Peak Shape를 관찰하여, AES를 이용하여 Ti 계열의 화합물에 대한 Chemical state 분석의 가능성을 평가하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.11
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• pp.683-689
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• 2015

For the formation of $N^+$ doping, the antimony ions are mainly used for the fabrication of a BJT (bipolar junction transistor), CMOS (complementary metal oxide semiconductor), FET (field effect transistor) and BiCMOS (bipolar and complementary metal oxide semiconductor) process integration. Antimony is a heavy element and has relatively a low diffusion coefficient in silicon. Therefore, antimony is preferred as a candidate of ultra shallow junction for n type doping instead of arsenic implantation. Three-dimensional (3D) profiles of antimony are also compared one another from different tilt angles and incident energies under same dimensional conditions. The diffusion effect of antimony showed ORD (oxygen retarded diffusion) after thermal oxidation process. The interfacial effect of a $SiO_2/Si$ is influenced antimony diffusion and showed segregation effects during the oxidation process. The surface sputtering effect of antimony must be considered due to its heavy mass in the case of low energy and high dose conditions. The range of antimony implanted in amorphous and crystalline silicon are compared each other and its data and profiles also showed and explained after thermal annealing under inert $N_2$ gas and dry oxidation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.562-565
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• 2001

In this paper, novel device structures in order to realize ultra fast and ultra small silicon devices are investigated using ultra-high vacuum chemical vapor deposition(UHVCVD) and Excimer Laser Annealing (ELA). Based on these fundamental technologies for the deep sub-micron device, high speed and low power devices can be fabricated. These junction formation technologies based on damage-free process for replacing of low energy ion implantation involve solid phase diffusion and vapor phase diffusion. As a result, ultra shallow junction depths by ELA are analyzed to 10~20nm for arsenic dosage(2${\times}$10$\_$14//$\textrm{cm}^2$), exciter laser source(λ=248nm) is KrF, and sheet resistances are measured to 1k$\Omega$/$\square$ at junction depth of 15nm and realized sub-50nm n-MOSFET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.349-352
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• 2001

In this paper, novel device structure in order to realize ultra fast and ultra small silicon devices are investigated using ultra-high vacuum chemical vapor deposition(UHVCVD) and Excimer Laser Annealing (ELA) for ultra pn junction formation. Based on these fundamental technologies for the deep sub-micron device, high speed and low power devices can be fabricated. These junction formation technologies based on damage-free process for replacing of low energy ion implantation involve solid phase diffusion and vapor phase diffusion. As a result, ultra shallow junction depths by ELA are analyzed to 10~20 nm for arsenic dosage (2$\times$10$^{14}$ $\textrm{cm}^2$), excimer laser source(λ=248nm) is KrF, and sheet resistances are measured to 1k$\Omega$/$\square$ at junction depth of 15nm.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.261-266
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• 1998

This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1$\mu\textrm{m}$ CMOSFETs using BF2 and arsenic as channel dopants. We have used and LDD structure and 40${\AA}$ gate oxide as an insulator. To suppress short channel effects down to 0.1$\mu\textrm{m}$ channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315${\mu}$S/$\mu\textrm{m}$, and that of pMOSFET is 156 ${\mu}$S/$\mu\textrm{m}$. The drain saturation current of 418 ${\mu}$A/$\mu\textrm{m}$, 187${\mu}$A/$\mu\textrm{m}$ are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000${\AA}$ thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.

• Korean Journal of Materials Research
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• v.1 no.1
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• pp.23-28
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• 1991

The resistivity of polycrystalline silicon film deposited by low pressure chemical vapor deposition and doped by arsenic Implantation has been investigated as a function of dopant concentration and testing temperature ranging from $25^{\circ}C$ to $105^{\circ}C$ . The resistivity vs. doping concentration curve had a peak point with highest activation energy with respect to the dependence of the resistivity on temperature. We showed that $O_2$ plasma anneal followed by heat-treatment in $N_2$ ambient was able to recover the resistivity degraded by the plasma deposited passivation layers.