• Title/Summary/Keyword: Low Cost Phase Shifter

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Application of GaAs Discrete p-HEMTs in Low Cost Phase Shifters and QPSK Modulators

  • Kamenopolsky, Stanimir D.
    • ETRI Journal
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    • v.26 no.4
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    • pp.307-314
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    • 2004
  • The application of a discrete pseudomorphic high electron mobility transistor (p-HEMT) as a grounded switch allows for the development of low cost phase shifters and phase modulators operating in a Ku band. This fills the gap in the development of phase control devices comprising p-i-n diodes and microwave monolithic integrated circuits (MMICs). This paper describes a discrete p-HEMT characterization and modeling in switching mode as well as the development of a low-cost four-bit phase shifter and direct quadrature phase shift keying (QPSK) modulator. The developed devices operate in a Ku band with parameters comparable to commercially available MMIC counterparts. Both of them are CMOS compatible and have no power consumption. The parameters of the QPSK modulator are very close to the requirements of available standards for satellite earth stations.

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Reflection-Type 5-bit Digital Phase Shifter with Constant Insertion Loss (균일 삽입 손실 특성을 갖는 반사형의 5-비트 디지털 위상 변위기)

  • 고경석;최익권
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.13 no.6
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    • pp.582-589
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    • 2002
  • This paper presents 12.2 GHz ~ 12.7 GHz frequency band reflection type 5-bit digital phase shifter with constant insertion loss property that was fabricated with relatively low cost's InGaAs HEMT for amplifier. The unavoidable large insertion loss difference between on and off states of HEMT, when it is designed by conventional design theory based on ideal switching device, is removed by transforming the HEMT impedances at on and off states to other proper values connecting a certain length transmission line to HEMT and then applying the conventional design theory. The fabricated 5-bit digital phase shifter shows very good insertion loss properties of less than 1.5 dB insertion loss difference and -4.5 dB ~ -6 dB insertion loss in 35 phase steps at 12.2 GHz ~ 12.7 GHz. These results verify the design method presented in this paper, which is useful to design phase shifter of constant insertion loss with non-ideal switching device.

Analog Ferrite Phase Shifter Using Substrate Integrated Waveguide (기판 집적 도파관을 이용한 아날로그 페라이트 위상 천이기)

  • Yim, Myung-Gyu;Byun, Jin-Do;Lee, Hai-Young
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.4
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    • pp.470-480
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    • 2011
  • Analog ferrite phase shifters based on rectangular waveguides which are used as component of passive phased array system have high power handling capability, but it is heavy and has high cost to fabricate. In this paper, we propose an analog ferrite phase shifter using substrate integrated waveguide(SIW), which has low cost and is easy to fabricate because it uses printed circuit board(PCB) process. The proposed structure is fabricated by using centeral dielectric material removal for inserting a ferrite bar. The measured results show that the proposed structure has not only $5.1^{\circ}$/mm phase variation but also return loss variation under 12.9 dB. Therefore, it is expected that the proposed phase shifter can plays an role to reduce weight and to has low cost on the phased array system.

Coupled Line Phase Shifters and Its Equivalent Phase Delay Line for Compact Broadband Phased Array Antenna Applications

  • Han, Sang-Min;Kim, Young-Sik
    • Journal of electromagnetic engineering and science
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    • v.3 no.1
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    • pp.62-66
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    • 2003
  • Novel coupled line phase shifters and its equivalent phase delay line for compact broadband phased array antennas are proposed. These phase control circuits are designed to be less complex, small size and to use a less number of active devices. The phase shifter is able to control a 120$^{\circ}$ phase shift continuously, and the phase delay line for a reference phase has a fixed 60$^{\circ}$ shifted phase. Both have the low phase error of less than $\pm$3.5$^{\circ}$ and the low gain variations of less than 1 ㏈ within the 300 MHz bandwidth. These proposed circuits are adequate to form the efficient beam-forming networks with compactness, broadband, less complexity, and low cost.

Small Broadband Phased Array Antenna with Compact Phase-Shift Circuits (간결한 위상 변위 회로를 갖는 소형 광대역 위상 배열 안테나)

  • 한상민;권구형;김영식
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.10
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    • pp.1071-1078
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    • 2003
  • In this paper, the planar, compact, and broadband phased array antenna system for IMT-2000 applications has been investigated. Two methods far designing a low-cost and low-complex beam-farming network are proposed. First, a new compact and broadband phase shifter with continuously controlled phase bits is designed by using parallel coupled lines. Second, its equivalent phase delay line is suggested to be capable of replacing the complex phase shifter with a reference phase bit on a phased array antenna. For the purpose of achieving the broadband system, in addition to the broadband phase shifter, a wide-slot antenna with a ground reflector is utilized as an element antenna. Therefore, the phased array antenna system has achieved compact size, broad bandwidth, and wide steering angle, although it has low complexity and low fabrication cost. The 3${\times}$1 phased array antenna system has a compact size of 1.6 λ${\times}$ l.6 λ, which is the sufficient ground plane of the wide-slot antenna. Experimental results present that the S$\_$11/ has less than 15 dB within the band and its radiation patterns on an E-plane have the capability of steering an antenna beam from -29$^{\circ}$to +30$^{\circ}$.

Filterless and Sensorless Commutation Method for BLDC Motors

  • Rad, Shahin Mahdiyoun;Azizian, Mohammad Reza
    • Journal of Power Electronics
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    • v.18 no.4
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    • pp.1086-1098
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    • 2018
  • This study presents a new sensorless commutation method for brushless direct current motors to replace Hall sensor signals with virtual Hall signals. The importance of the proposed method lies in the simultaneous elimination of the phase shifter and the low-pass filters, which makes the method simple and cost-effective. The method removes high ripple switching noises from motor terminals, thereby decreasing motor losses. The proposed method utilizes unfiltered line voltages with notches caused by current commutation. Hence, specific sign signals are defined to compensate for the effects of commutation noise. The proposed method is free from phase delay that originates from low-pass filters. The method directly produces virtual Hall signals, and thus, it can be interfaced with low-cost commercial commutation integrated circuits based on Hall sensors. Simulation and experimental results show the effectiveness and validity of the proposed method.

Design and Implementation of 40 Gb/s Clock Recovery Module Using a Phase-Locked Loop with hold function (유지 기능을 가지는 위상고정 루프를 이용한 40 Gb/s 클락 복원 모듈 설계 및 구현)

  • Park, Hyun;Woo, Dong-Sik;Kim, Jin-Joog;Lim, Sang-Kyu;Kim, Kang-Wook
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2005.11a
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    • pp.191-196
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    • 2005
  • A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver has been designed and implemented. It consists of a clock recovery circuit, a RF mixer and frequency discriminator for phase/frequency detection, a DR-VCO, a phase shifter, and a hold circuit. The recovered 40 GHz clock is synchronized with a stable 10 GHz DR-VCO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module has shown to significantly improve the performance of the conventional open-loop type clock recovery module with DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When input signal is dropped, the 40 GHz clock is generated continuously by hold circuit. The implemented clock recovery module can be used as a low-cost and high-performance receiver module for 40 Gb/s commercial optical network.

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The radar development of the low output using the phased array antenna (위상 배열 안테나를 이용한 저출력의 레이더 개발)

  • Cho, Dae-young;Kim, Jeong-hwan;Lee, Myoung-won;Lee, Ju-Hyoung;Lim, Tae-Ho;Yoon, Won-Sang;Ko, Hak-Lim
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.5
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    • pp.913-920
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    • 2017
  • In this development, By using the phase array antenna, the beam around was electronically revolved and the marine fixed type radar of which the detection is possible was made and the check around was tested. There are the risk of the corrosion because of the abrasion of the axis of rotation and salinity with the way that the existing marine pulse radar detects the check by using the mechanical rotation. Besides, the maintenance cost of the magnetron gets to happen by using the detection signal. In this development, The fixed type radar of the low output which revolves electronically around the beam by using the radar signal processing method of the phase array antenna using the phase shifter and FMCW(Frequency Modulation Continuous Wave) method was made. And by using the fixed type radar, the check detection test was conducted.

Design and Implementation of a 40 Gb/s Clock Recovery Module Using a Phase-Locked Loop with the Clock-Hold Function (클락 유지 기능을 가지는 위상 고정 루프를 사용한 40 Gb/s 클락 복원 모듈 설계 및 구현)

  • Park Hyun;Woo Dong-Sik;Kim Jin-Jung;Lim Sang-Kyu;Kim Kang-Wook
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.17 no.2 s.105
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    • pp.171-177
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    • 2006
  • A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver with the clock-hold function has been designed and implemented. It consists of a clock extractor circuit, an RF mixer and a frequency discriminator for phase/frequency detection, a VC-DRO, a phase shifter, and a clock-hold circuit. The extracted 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module are significantly improved as compared with those of the conventional open-loop type clock recovery module with a DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When an input signal is dropped, the 40 GHz clock is maintained continuously by the hold circuit.