• Journal of Power Electronics
• /
• v.11 no.1
• /
• pp.59-63
• /
• 2011

This paper presents the modeling of the sampling effect in the p-type average current mode control. The prediction of the high frequency components near half of the switching frequency in the current loop gain is given for the p-type average current mode control. By the proposed model, the prediction accuracy is improved when compared to that of conventional models. The proposed method is applied to a buck converter, and then the measurement results are analyzed.

• 제어로봇시스템학회:학술대회논문집
• /
• 1993.10b
• /
• pp.385-390
• /
• 1993

It is the purpose of this paper to present a dialogical tuning method of the sampling period in fuzzy control systems. Last year, the authors gave a dialogical tuning technique of fuzzy control system under the fixed sampling period in this symposium. In the case where sampling period is chosen larger, the response of the control system is unsatisfactory, and in the case where the sampling period is smaller, ineffective control actions are repeated. The appropriate sampling period is chosen through the step response of the closed loop fuzzy control process. As the tuning technique depends on the controlled plant, it is necessary to estimate the rough characteristics of it. The authors propose a method to decide th appropriate sampling period, by inspecting the characteristics of the plant.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.2C
• /
• pp.191-200
• /
• 2002

A frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop) in this paper. For improving phase noise characteristic two loops, reference loop and main loop, were divided. Phase noise was improved by transformed clamp type voltage controled oscillator and optimizing loop bandwidth in reference loop. And voltage controlled oscillator open loop gain in main loop. Fabricated the frequency synthesizer had 1.81GHz center frequency, 160MHz tuning range, 13.5dBm output power and -119.73dBc/Hz low phase noise characteristic.

• Smart Structures and Systems
• /
• v.16 no.6
• /
• pp.1147-1167
• /
• 2015

Wireless smart sensors, which have become popular for monitoring applications, are an attractive option for implementing structural control systems, due to their onboard sensing, processing, and communication capabilities. However, wireless smart sensors pose inherent challenges for control, including delays from communication, acquisition hardware, and processing time. Previous research in wireless control, which focused on semi-active systems, has found that sampling rate along with time delays can significantly impact control performance. However, because semi-active systems are guaranteed stable, these issues are typically neglected in the control design. This work achieves active control with smart sensors in an experimental setting. Because active systems are not inherently stable, all the elements of the control loop must be addressed, including data acquisition hardware, processing performance, and control design at slow sampling rates. The sensing hardware is shown to have a significant impact on the control design and performance. Ultimately, the smart sensor active control system achieves comparable performance to the traditional tethered system.

• Journal of the Computational Structural Engineering Institute of Korea
• /
• v.17 no.2
• /
• pp.151-160
• /
• 2004

In the present study, Loop scheme is applied to generate smooth surfaces. To be consistent with the limit points of target surface, the initial sampling points are properly rearranged. The pointwise errors of curvature and position in the sequence of subdivision process are evaluated in the Loop subdivision scheme. A first-order shear deformable Loop subdivision triangular element which can handle transverse shear deformation of moderately thick shell are developed. The developed element is more general than the previous one based on classical shell theory, since the new one includes the effect of transverse shear deformation and has standard six degrees of freedom per node. The quartic box spline function is used as interpolation basis function. Numerical examples for the benchmark static shell problems are analyzed to assess the performance of the developed subdivision shell element and locking trouble.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.12 no.5
• /
• pp.478-491
• /
• 1987

In this paper, an all Digital Phase-Locked Loop(DPLL) has been propoed, which has reduced the phase error by using a half period sampling in order to improve the performance of the conventional DPLL which tracks the phase of incoming sinusoidal signal once per cycle for the Positive Going Zero crossing(PGZC) of the signal. The proposed DPLL tracks the phase of input signal twice per cycle with two samplers for the PGZC. So the loop has a half reduction of the steady state phase error fluctuation ranges without decreasing the lock-range in a whole, comparing with that of the conventional DPLL. Also, it has been known that the proposed loop is rapidly locked to input signal for the same valves of phase differenc between sucessive samples and quantization level. The analytic results of the proposed loop have been verified by computer simulation for the practically requeired conditions.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
• /
• v.2
• /
• pp.385-390
• /
• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.7B
• /
• pp.916-927
• /
• 2001

본 논문에서는 인터넷 환경에서 멀티미디어의 동기를 맞추어 주기 위하여 가상 클럭(VGC : Virtual Global Clock)을 구성하였고, 가상 클락 기반의 SRTS를 제안하여 미디어 내부 동기(sntra_synchronization)를 이루었다. 8bit/8kHz PCM-sampling 음성 신호에서 320byte를 한 프레임으로 했을 때 각 프레임에 순서 번호를 넣어서 미디어간의 동기(inter_synchronization)를 유지한다. Loop Back 방법을 이용하여 구성한 가상 클럭(VGC)은 통신이 가능한 모든 환경에 적용할 수 있다.

• 제어로봇시스템학회:학술대회논문집
• /
• 1986.10a
• /
• pp.298-303
• /
• 1986

A robust and efficient dynamic control algorithm for the position control of robotic manipulators is proposed. This algorithm consists of an open loop control and a closed loop control. The former may have a larger sampling time than the latter. The robustness and efficiency of this algorithm is demonstrated by the simulation about position control of a three-link manipulator with payload and parameter uncertainty.

• 제어로봇시스템학회:학술대회논문집
• /
• 2000.10a
• /
• pp.360-360
• /
• 2000

In this paper, a new criterion f9r determining the sampling rate of digital conroller is proposed. This paper will introduce a method fur determining the appropriate sampling rate of digital controller which can be substituted with the given analog controller, using phase margin and gain cross over frequency, not rising time or bandwidth of the closed-loop system. This method also guarantees performance of the system. Without exact modeling functions of the plant, abstracting those functions, this paper can achieve stability and aimed performance of the system, and this paper proved it with proper modeling functions.