• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.35-44
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• 2002

In this paper, an implementation method of RSA exponentiator based on Radix-$2^k$ modular multiplication algorithm is presented and verified. We use Booth receding algorithm to implement Radix-$2^k$ modular multiplication and implement radix-16 modular multiplier using 2K-byte memory and CSA(carry-save adder) array - with two full adder and three half adder delays. For high speed final addition we use a reduced carry generation and propagation scheme called pseudo carry look-ahead adder. Furthermore, the optimum value of the radix is presented through the trade-off between the operating frequency and the throughput for given Silicon technology. We have verified 1,024-bit RSA processor using Altera FPGA EP2K1500E device and Samsung 0.3$\mu\textrm{m}$ technology. In case of the radix-16 modular multiplication algorithm, (n+4+1)/4 clock cycles are needed and the 1,024-bit modular exponentiation is performed in 5.38ms at 50MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.788-795
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• 2000

Scattered look-ahead pipelining method can be efficiently used for high sample rate or low-power applications of digital recursive filters. Although the pipelined filters are guaranteed to be stable by this method, these filters suffer from large round off noise when the poles are crowed within some critical regions. To avoid this problem, a low-noise implementation technique was proposed using constrained Remez exchange algorithm. By the constrained filter design approach, the desired filter spectrum is satisfied while some of the pole angles are constrained to avoid pole crowding within critical regions. In the proposed approach, to obtain improved spectrum characteristics or better round off noise properties, the radius of the angle-constrained pole is optimized depending on the direction of the pole movement.

• Journal of applied mathematics & informatics
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• v.17 no.1_2_3
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• pp.457-473
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• 2005

In each step of the quasi-minimal residual (QMR) method which uses a look-ahead variant of the nonsymmetric Lanczos process to generate basis vectors for the Krylov subspaces induced by A, it is necessary to decide whether to construct the Lanczos vectors $v_{n+l}\;and\;w{n+l}$ as regular or inner vectors. For a regular step it is necessary that $D_k\;=\;W^{T}_{k}V_{k}$ is nonsingular. Therefore, in the floating-point arithmetic, the smallest singular value of matrix $D_k$, ${\sigma}_min(D_k)$, is computed and an inner step is performed if $\sigma_{min}(D_k)<{\epsilon}$, where $\epsilon$ is a suitably chosen tolerance. In practice it is absolutely impossible to choose correctly the value of the tolerance $\epsilon$. The subject of this paper is to show how discrete stochastic arithmetic remedies the problem of this tolerance, as well as the problem of the other tolerances which are needed in the other checks of the QMR method with the estimation of the accuracy of some intermediate results. Numerical examples are used to show the good numerical properties.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.125-136
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• 2009

This paper presents a high-speed low-complexity two-bit level pipelined Viterbi decoder architecture for MB-OFDM UWB systems. As the add-compare-select unit (ACSU) is the main bottleneck of the Viterbi decoder, this paper proposes a novel two-bit level pipelined MSB-first ACSU, which is based on 2-step look-ahead techniques to reduce the critical path. The proposed ACSU architecture requires approximately 12% fewer gate counts and 9% faster speed than the conventional MSB-first ACSU. The proposed Viterbi decoder was implemented with $0.18-{\mu}m$ CMOS standard cell technology and a supply voltage of 1.8V. It operates at a clock frequency of 870 MHZ and has a throughput of 1.74 Gb/s.

• The KIPS Transactions:PartA
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• v.12A no.1 s.91
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• pp.7-12
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• 2005

Scattered look-ahead(SLA) pipelining method can be efficiently used for high-speed or low-power applications of digital II R filters. Although the pipelined filters are guaranteed to be stable by this method, these filters suffer from large roundoff noise when the poles are crowded within some critical regions. An angle and radius constrained II R fille. design approach using modified Remez exchange algorithm and least squares algorithm is proposed to avoid tight pole-crowding in pipelined filters, resulting in improved frequency responses and reduced coefficient sensitivities. Experimental results demonstrate that our proposed method leads to chip area reduction by $33{\%}$ and low power by $45{\%}$ against the conventional method.

• Journal of the Korean Operations Research and Management Science Society
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• v.22 no.2
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• pp.79-97
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• 1997

Many dispatching rules have been developed for the on-line control of product flow in a job shop. The introduction of a flexible manufacturing system (FMS) has added a new requirement to classical job shop control problem : the selection of machines by parts of different types. An FMS can keep a great deal of information on the status of the system, such as information on what is scheduled in the near future, with great accuracy. For example, the knowledge of the time when the next part will arrive at each machine can be neneficial for the routing. This paper tests the effects of the use of this knowledge for part routing on the parts flow time (sum of the time for waiting and service) under a simple routing procedure- a look-ahead routing procedure. A test under many operating conditions shows that the reduction of part flow time from the cases without using this information is between 1% and 11%, which justifies more study on this routing procedure at real production sites when machine capacity is a critical issue. The test results of this paper are also valid for other highly automated systems such as the semi-conductor fabrication plants for routing when the arrivals of parts in the near future are known.

• Journal of the Korea Society for Simulation
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• v.21 no.4
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• pp.1-9
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• 2012

This paper suggests a two-phase look-ahead Banker's algorithm for efficient operation of capacitated automated production systems. The algorithm improves the ability of detecting safe states of the previous one by considering the possibility of processing each job to completion at once as well as partial movement between jobs. The improved performance of the proposed algorithm is testified by performing numerical experiment in terms of (i) detection rate of safe states and (ii) system throughput and verified by using paired t-test.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.4
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• pp.91-96
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• 2001

In this paper we propose a new ENMODL(Enhanced-NORA-MODL) CLA(Carry-Look Ahead Adder) for high speed and low power multiplier. To reduce transistor counts, area and power dissipation we developed new-approaches. The method makes use of a dynamic CMOS logic ENMODL CLA. The advantage of ENMODL is small area and high speed The speed of ENMODL CLA is invreased by 6.27 % as compared with conventional NMOCL CLA. The proposed method was verified by HSPICE simulation and layout througth 0.6${\mu}{\textrm}{m}$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.10 s.340
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• pp.25-30
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• 2005

This paper generalizes the concept of the signal space detection to construct a fixed delay tree search (FDTS) detector which estimates a block of n channel symbols at a time. This technique is applicable to high speed implementation. Two approaches are discussed both of which are based on efficient signal space partitioning. In the first approach, symbol detection is performed based on a multi-class partitioning of the signal space. This approach is a generalization of binary symbol detection based on a two-class pattern classification. In the second approach, binary signal detection is combined with a look-ahead technique, resulting in a highly parallel detector architecture.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3181-3183
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• 1999

A CMOS two-stage oscillator applicable to requiring in- and quadrature-phase components such as RF and data retiming applications are presented using phase-look-ahead technique. This paper clearly describes the operation principle of the presented two-stage oscillator and the principle can be also applicable to the high speed high speed divide-by-two is usually used for prescaler of the frequency synthesizer. Also, the sucessful oscillation of the proposed oscillator using PLA is confirmed through the experiment. The test vehicle is designed using 0.8 ${\mu}m$ N-well CMOS process and it has a maximum 914MHz oscillation showing -75dBclHz phase noise at 100kHz offset with single 2V supply.