• 반도체디스플레이기술학회지
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• 제2권4호
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• pp.1-7
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• 2003

In this paper, we design the pattern generator circuits using PLDs(Programmable Logic Devices). The pattern generator is the circuit which generates the test pattern signal for the inspection of logical defects of semiconductor products. The proposed circuits are designed by the PLD design tool(MAX+ II of ALTERA). Also the designed circuits are simulated for the verification of the designed ones. The simulation results have a good performance.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1980-1983
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• 2002

When a feedback bridging fault is activated in a circuit, logical oscillation may occur at a signal line. If the oscillation appears, the fault may not be detected by logic testing. In order to detect such bridging faults, output logic values of the circuit should be measured at higher frequency than frequency of the logical oscillation. In this paper, a method fur estimating the maximum frequency of logical oscillation is proposed to detect such bridging faults in a circuit by logic testing. Also, it is shown by some experiments that such bridging faults can be detected by measuring output logic values at the frequency obtained by the method.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1996년도 Proceedings of the Korea Automatic Control Conference, 11th (KACC); Pohang, Korea; 24-26 Oct. 1996
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• pp.279-282
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• 1996

The authors have already proposed a method for grouping of inputs of a logical circuit under test (LCUT) by use of M-sequence correlation. We call this method as input grouping (IG) method. In this paper, the authors propose a new method to estimate the faulty part in the circuit by use of IG when some information on the candidate of faulty part can be obtained beforehand. The relationship between IG and fault probabilities of a LCUT, and undetected fault ratios are investigated for various cases. Especially the investigation was made in case where the IG was calculated by use of n correlation functions (I $G_{inp}$). From the theoretical study and simulation results it is shown that the estimation error ratio of fault probabilities and undetected fault ratio of LCUT are sufficiently small even when only a part of correlation functions are used. It is shown that the number of correlation functions which are to be memorized to calculate IG can be considerably reducible from 2$^{n}$ - 1 to n by use of I $G_{inp}$. So this method would be very useful for a fault diagnosis of actual logic circuit.uit.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1992년도 한국자동제어학술회의논문집(국제학술편); KOEX, Seoul; 19-21 Oct. 1992
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• pp.569-572
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• 1992

This paper describes a new method of pseudorandom testing of a digital circuit by use of correlation method and a neural network. The authors have recently proposed a new method of fault diagnosis of logical circuit by applying a pseudorandom M-sequence to the circuit under test, calculating the crosscorrelation function between the input and the output, and comparing the crosscorrelation functions with the references. This method, called MSEC method, is further extended by using a neural network in order to not only detect the existence of faults but also find the place or location of the faults. An experiment by using a simple digital circuit shows enough applicability of this method to industrial testing of circuit board.

• 산업경영시스템학회지
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• 제19권37호
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• pp.9-20
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• 1996

The writer has made efforts to solve the weaknesses of the traditional systems through reconstructing cost information systems by introducing 'logical circuit concept' instead of account. As the new designed systems also allow the basic thought of double entry, they are compatiable with the traditional ones. For this, the writer included both monetary and physical information in the systems, replaced the concept of debit & credit with the concept of inputs & outputs, and changed transfer concept between accounts based on reverse logic into flow concept between unit systems based on proceeding logic.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1995년도 Proceedings of the Korea Automation Control Conference, 10th (KACC); Seoul, Korea; 23-25 Oct. 1995
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• pp.146-149
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• 1995

A new method for grouping of relevant and equivalent inputs of a logical circuit was proposed by the authors by making use of pseudorandom M-sequence correlation. The authors show in this paper that it is possible to estimate the input grouping from a part of correlation functions when we admit small percentage of error, whereas it is impossible to reduce the data necessary to estimate the grouping by use of the truth table method. For example in case of 30-input logic circuit, the number of correlation functions necessary to calculate can be reducible from 1.07 * 10$^{9}$ to 465.

• ETRI Journal
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• 제45권3호
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• pp.462-478
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• 2023

In quantum computing, the use of Pauli frames through software traces of classical computers improves computation efficiency. In previous studies, error correction and Pauli operation tracking have been performed simultaneously using integrated Pauli frames in the physical layer. In such a complex processing structure, the number of simultaneous operations processed in the physical layer exponentially increases as the distance of the surface code encoding logical qubit increases. This study proposes a Pauli frame management architecture partitioned into two layers for a lattice surgery-based surface code and describes its structure and operation rules. To evaluate the effectiveness of our method, we generated a random circuit according to the gate ratios constituting the commonly known quantum circuits and compared the generated circuit with the existing Pauli frame and our method. Simulations show a decrease of about 5% over traditional methods. In the case of experiments that only increase the code distance of the logical qubit, it can be seen that the effect of reducing the physical operation through the logical Pauli frame becomes more important.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2011년도 정기총회 및 추계학술대회 논문집
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• pp.2726-2730
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• 2011

This paper proposes a CBTC wayside signaling system, which redeems existing track-circuit-based ones by using movement authorities mixed with logical block and moving block. Only one train can be entered into the logical block or the route for existing wayside signaling system. Applying moving block for CBTC system enables the train to get nearer to the preceding one, because its protection mechanism uses train's safe boundary, not fixed block unit. By narrowing the existing route set to switch machine and applying the moving block beyond that area, more than one train can enter into one route area. This paper shows that the efficient train control, i.e. shortening the headway, is possible using the moving block mixed with logical block in wayside signaling system.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제2권3호
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• pp.103-110
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• 2013

논리 노력[1, 2]의 기법은 회로의 지연 값을 간단한 필산으로 신속하게 측정할 수 있는 기술이다. 이 기법은 설계 공정 시간을 절약하는 장점도 있지만 고정 지연이라는 조건에서 논리 경로의 면적이나 전력 소비를 최소화하여 설계할 수 없는 단점이 있다. 이 단점을 보완하는 방법을 논문[3]에서 제안하였지만, 논리 경로가 하나인 회로에만 국한되어 적용할 수 있는 방법이었다. 본 논문에서는, 균형 지연 모델을 기초로, 다중 논리 경로의 회로에 적용할 수 있는 향상된 게이트 크기 결정 방법을 제한하고자 한다. 시뮬레이션 결과, 기존 논리노력 방법과 비교하면 전력 소비 측면에서 거의 같았지만 회로의 설계 공간 측면에서는 약 52%의 효율성을 보였다.

• 한국컴퓨터산업학회논문지
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• 제7권3호
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• pp.205-215
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• 2006

본 논문에서는 최근의 64비트 마이크로프로세서에 대해서 PLA설계법 및 검사가 쉽고 용이하도록 하는 방법에 대해서 논하였다. VLSI에서 RAM. ROM. PLA를 사용한 설계법이 정착 되어가고 있으며 PLA는 논리설계와 회로변경 및 검사가 용이하기 때문에 성능과 가격이 중요하다. 향후에도 PLA는 VLSI 설계의 기본요소로서 중요한 위치를 점유할 것이다.