• Journal of the Semiconductor & Display Technology
• /
• v.2 no.4
• /
• pp.1-7
• /
• 2003

In this paper, we design the pattern generator circuits using PLDs(Programmable Logic Devices). The pattern generator is the circuit which generates the test pattern signal for the inspection of logical defects of semiconductor products. The proposed circuits are designed by the PLD design tool(MAX+ II of ALTERA). Also the designed circuits are simulated for the verification of the designed ones. The simulation results have a good performance.

• Proceedings of the IEEK Conference
• /
• 2002.07c
• /
• pp.1980-1983
• /
• 2002

When a feedback bridging fault is activated in a circuit, logical oscillation may occur at a signal line. If the oscillation appears, the fault may not be detected by logic testing. In order to detect such bridging faults, output logic values of the circuit should be measured at higher frequency than frequency of the logical oscillation. In this paper, a method fur estimating the maximum frequency of logical oscillation is proposed to detect such bridging faults in a circuit by logic testing. Also, it is shown by some experiments that such bridging faults can be detected by measuring output logic values at the frequency obtained by the method.

• 제어로봇시스템학회:학술대회논문집
• /
• 1996.10a
• /
• pp.279-282
• /
• 1996

The authors have already proposed a method for grouping of inputs of a logical circuit under test (LCUT) by use of M-sequence correlation. We call this method as input grouping (IG) method. In this paper, the authors propose a new method to estimate the faulty part in the circuit by use of IG when some information on the candidate of faulty part can be obtained beforehand. The relationship between IG and fault probabilities of a LCUT, and undetected fault ratios are investigated for various cases. Especially the investigation was made in case where the IG was calculated by use of n correlation functions (I $G_{inp}$). From the theoretical study and simulation results it is shown that the estimation error ratio of fault probabilities and undetected fault ratio of LCUT are sufficiently small even when only a part of correlation functions are used. It is shown that the number of correlation functions which are to be memorized to calculate IG can be considerably reducible from 2$^{n}$ - 1 to n by use of I $G_{inp}$. So this method would be very useful for a fault diagnosis of actual logic circuit.uit.

• 제어로봇시스템학회:학술대회논문집
• /
• 1992.10b
• /
• pp.569-572
• /
• 1992

This paper describes a new method of pseudorandom testing of a digital circuit by use of correlation method and a neural network. The authors have recently proposed a new method of fault diagnosis of logical circuit by applying a pseudorandom M-sequence to the circuit under test, calculating the crosscorrelation function between the input and the output, and comparing the crosscorrelation functions with the references. This method, called MSEC method, is further extended by using a neural network in order to not only detect the existence of faults but also find the place or location of the faults. An experiment by using a simple digital circuit shows enough applicability of this method to industrial testing of circuit board.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.19 no.37
• /
• pp.9-20
• /
• 1996

The writer has made efforts to solve the weaknesses of the traditional systems through reconstructing cost information systems by introducing 'logical circuit concept' instead of account. As the new designed systems also allow the basic thought of double entry, they are compatiable with the traditional ones. For this, the writer included both monetary and physical information in the systems, replaced the concept of debit & credit with the concept of inputs & outputs, and changed transfer concept between accounts based on reverse logic into flow concept between unit systems based on proceeding logic.

• 제어로봇시스템학회:학술대회논문집
• /
• 1995.10a
• /
• pp.146-149
• /
• 1995

A new method for grouping of relevant and equivalent inputs of a logical circuit was proposed by the authors by making use of pseudorandom M-sequence correlation. The authors show in this paper that it is possible to estimate the input grouping from a part of correlation functions when we admit small percentage of error, whereas it is impossible to reduce the data necessary to estimate the grouping by use of the truth table method. For example in case of 30-input logic circuit, the number of correlation functions necessary to calculate can be reducible from 1.07 * 10$^{9}$ to 465.

• ETRI Journal
• /
• v.45 no.3
• /
• pp.462-478
• /
• 2023

In quantum computing, the use of Pauli frames through software traces of classical computers improves computation efficiency. In previous studies, error correction and Pauli operation tracking have been performed simultaneously using integrated Pauli frames in the physical layer. In such a complex processing structure, the number of simultaneous operations processed in the physical layer exponentially increases as the distance of the surface code encoding logical qubit increases. This study proposes a Pauli frame management architecture partitioned into two layers for a lattice surgery-based surface code and describes its structure and operation rules. To evaluate the effectiveness of our method, we generated a random circuit according to the gate ratios constituting the commonly known quantum circuits and compared the generated circuit with the existing Pauli frame and our method. Simulations show a decrease of about 5% over traditional methods. In the case of experiments that only increase the code distance of the logical qubit, it can be seen that the effect of reducing the physical operation through the logical Pauli frame becomes more important.

• Proceedings of the KSR Conference
• /
• 2011.10a
• /
• pp.2726-2730
• /
• 2011

This paper proposes a CBTC wayside signaling system, which redeems existing track-circuit-based ones by using movement authorities mixed with logical block and moving block. Only one train can be entered into the logical block or the route for existing wayside signaling system. Applying moving block for CBTC system enables the train to get nearer to the preceding one, because its protection mechanism uses train's safe boundary, not fixed block unit. By narrowing the existing route set to switch machine and applying the moving block beyond that area, more than one train can enter into one route area. This paper shows that the efficient train control, i.e. shortening the headway, is possible using the moving block mixed with logical block in wayside signaling system.

• KIPS Transactions on Computer and Communication Systems
• /
• v.2 no.3
• /
• pp.103-110
• /
• 2013

Logical Effort [1, 2] is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. However, it has shortcomings in designing a path for minimum area or power under a fixed-delay constraint. The method of overcoming the shortcomings is shown in [3], but it is constrained for a single logical path. This paper presents an advanced gate sizing method in multiple logical paths based on the equal delay model. According to the results of the simulation, the power dissipation for both the existing logical effort method and proposed method is almost equal. However, compared with the existing logical effort method, it is about 52 (%) more efficient in space.

• Journal of the Korea Computer Industry Society
• /
• v.7 no.3
• /
• pp.205-215
• /
• 2006

In this paper, a method how to make Programmable Logic Array (PLA) design and inspection of circuit relative to recent 64bit microprocessor simple and easy was discussed. A design method using Random Access Memory (RAM), Read Only Memory (ROM) and PLA has been settled down in Very Large Scale Integrated Circuit (VLSI) and logical design, modifying circuit and inspection are easy in PLA so it holds fairly good advantages in the aspect of performance and cost. It is expected PLA will also occupy an important position as a basic factor in designing VLSI in the future.