• Journal of the Korean Institute of Landscape Architecture
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• v.36 no.6
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• pp.1-11
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• 2009

This study focuses on Abstract Types in Contemporary Landscape Design. The formation and artistry of contemporary landscape design reveals many areas which Previously have not been able to be expressed in scenic landscape thanks to the deviation of the genre in contemporary landscape and the hybridization that has occurred among architecture, landscape and art genres. The focus of this study is basic research concerning "the abstract", which is used as a creative artistic theory in a variety of art fields such as landscape, architecture and painting. Through a theoretical establishment of "the abstract", its process of change, and the discovery of its contemporary principles, the relationship between each art field in landscapes and the formation of the abstract, abstract language, and abstract properties have been studied. The use of the abstract in contemporary landscape design can be classified in three ways: Inductive abstract representing conceptual transcendental symbols not logically but rather through intuition and transcendental cognition to display the inner expressions, ideas and minds of the artists. Second, a deductive abstract represents an expansive, logical model for the simplification of objects, distortion, exaggeration based on knowledge and logical reasoning about objective fact based on traditional realism. The complexity of the abstract is a concept that is bound to both the deductive & inductive abstract. As a major trend, the concept of "The abstract" in contemporary landscape has been putting forth ever-deeper roots. New trends like abstract works and landscape architecture reflecting the artist's inner expression, in particular, will provide fertile soil for landscape in the future. Further research about the concept of "the abstract" will also be necessary in the time to come.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• The Journal of the Korea Contents Association
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• v.12 no.8
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• pp.1-12
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• 2012

We develop the Spatio-Temporal Graph to imbue the historical context to the situations in a virtual world, and an ontology to enable a structural description of their elements such as the objects, relationships, and activities. In the time dimension the graph models all the temporal phases of the future besides the past and present in a comprehensive manner, and all the spatial aspects in an intuitive but efficient fashion. The overall architecture composing the Physical Layer, Logical Layer and Conceptual Layer which are integrated according to their interrelations allows events occurring in their corresponding worlds to be simulated in historical context. The S-T Graph could be used both to simulate the situations in the virtual world and to realize the knowledge systems of the virtual inhabitants to be used in judging and evaluating those situations. By adding temporal changes to the multi-layered architecture of our virtual world, this model lays a foundation for maximizing the diversity of situations in the simulation of a virtual world.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.1
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• pp.45-52
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• 2020

This paper proposes a solution for storage and retrieval problems for Resource Description Framework (RDF) data utilizing a key-value Solid State Device (SSD), considering storage, retrieval performance, and security. We propose a two-step compression algorithm to separate logical relationship and true values from RDF data-sets using the key-value SSD. This improves not only compression and storage efficiency but also storage security. We also propose a hybrid retrieval structure based on R∗-tree to enhance retrieval efficiency and implement a sort-merge join algorithm, and discuss factors affecting R∗-tree retrieval efficiency. Finally, we show the proposed approach is superior to current compression, storage, and retrieval approaches, obtaining target results faster while requiring less space, and competitive in terms of versatility, flexibility and security.

• Journal of The Korean Digital Architecture Interior Association
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• v.1 no.1
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• pp.59-66
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• 2001

The purpose of this study is to improve productivity of architectural space planning(A.S.P,) by computer system and to optimize ASP. A searching algorithm is the best way to slave optimized A.S.P. Because architectural design is too many various site situations and client's demands to specify the general solving methods. This method seek the best design case in all possibility and to be modeled as this; Seongbukgu's case that is city structure former times negative by in facilities utilization of the near street limit. But, case of Gangnamgu and Songpagu is thought that environment and utilization etc. of area life of old people are affinity with quality of life environment of old people when see that is using various area facilities using electric railway and a bus etc. actively. It is looked by the other that individual's special quality uses area facilities according to life partner's existence and nonexistence and family composition and existence and nonexistence of profession and distinction of sex. Show difference of external behavior according to public garden and market and supermarket and welfare facilities etc.'s location in dwelling environment of area and relation about facilities of area has been formed and old people and dwelling environment of area can know that is that do interaction. Environment that access about facilities may have to be easy, and can live that communicating closely with area's inhabitantses may have to consist so that old people may can run various external life.. Notions of the evaluated value is an profit(+) and expense(-) that decide design intention. To adapt real planning, 1. A raster type space cell has logical site informations. 2. To be evaluate various factor. 3. To reflect operator's design mind, they should add an extra weight on evaluated value.

• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.961-968
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• 1996

In the frame of Koreasat Project, it has been identified the task to implement a pilot satellite network module to provide LAN-to-LAn in ground system for satellite links. The pilot network will support an experiment to verify the performances of the considered applications through a satellite.This paper proposes a satellite-LAN interconnecting architecture making full use of satellite benefits and counteracting satellite demerits. The architectureprovides high quality data transmission and high perfrmance for satellite bit errors by using a connection- oriented satellite protocol which can establish multiple logical links between two nodes. As a protocol conversion method, router-type interconnection was selected to guard against problems. Based on this architecture, a satellite LAN interconnecting system has been designed, which includes a 1.8 meter antenna with a 4 watt transceiver, a satellite modem and the developed satellite network interface. The system can support high speed transmission rates of up to 1.544 Mbs and superior network management as well.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1697-1706
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• 1996

This paper presents the design and the implementation of a MissCW(Multi user Interactive System for Synchronous Collaborative Writing). The document model DMDA(Distributed Multimedia Document Architecture) of MissCW consists of the logical structure, presentation style object, and mark object. The windows. The collaborative editor of this system proposes a structure oriented editing mechanism to combine distrbuted objects into one document. The middleware SOM(Shared Object Manager) maintains shared objects consistently and helps application programs use objects efficiently. The infrastructure of this system is a hybrid structure of replicated and centralized architectures, that is to maintain shared objects consistently inside of SOM and to reduce the overhead of network traffic. The central part is a virtual node which corresponds to the Object Controller of SOMwith the SOT(Shared Objet Table).

• Journal of Korean Society of Rural Planning
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• v.17 no.3
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• pp.55-65
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• 2011

Long distance trail or trail system planning is the first important step in transforming your vision into reality. Planning presents a vision for a trail or trail system and brings a comprehensive, long-range perspective. The master plan provides solid, credible recommendations for developing a trail or trail system that is safe, convenient, well used, supported by local residents, practicality to implement, and customized to meet the needs of the community, you will need to follow a logical planning. The key elements of master planning includes site assessment, vision, goals and objectives, routing and design, implementation strategies. Trails or trail systems should provide linkages to popular destinations, safely accommodate a variety of users, and be sensitive to any negative impacts on the natural environment and wildlife. Trails planners also need to think about how the trail, or trail system will function in the future as areas are developed or trail population increases. All of these factors during the planning process will ensure the existence of high-quality facilities for years to come. Project for Nakdong-jungmaek trail planning combine long distance trail with circuit way. That project is a planning brought out the best in each of Tokai natural way and Cotswold way. That is planning which is combined a wooded trail in Tokai natural way with access and facilities improving economy in Cotswold way. Also That planning embraces a core cultural center which is concerned forest or wood to come more people.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.7
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• pp.425-432
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• 2014

This paper proposes a wear-leveling algorithm that exploits the properties of SSD memories with multi-channel and multi-way architecture. When a write request arrives, the proposed algorithm classifies the stored data in DRAM buffer into hot or cold according to logical address access frequency, and performs data allocation to reduce deviation of block erase counts. It lowers the chance of increasing erase count by allocating cold data to blocks which have high erase count. Effectiveness of the proposed algorithm is verified by executing various applications on a multi-channel, multi-way SSD simulator. Experimental results show that differences in erase count among blocks is reduced by an average of 9.3%, and total erase count decreases by 4.6%, when compared to previous wear-leveling algorithm.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.23-30
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• 2006

This paper presents design andd verification of a circuit that improves the control-operation problems of Stored Program Optical Computer (SPOC), which is an optical computer using $LiNbO_3$ optical switching element. Since the memory of SPOC takes the Delay Line Memory (DLM) architecture and instructions that are needless of operands should go though memory access stages, SPOC memory have problems; it takes immoderate access time and unnecessary operations are executed in Arithmetic Logical Unit (ALU) because desired operations can't be selectively executed. In this paper, improvement on circuit has been achieved by removing the memory access of instructions that are needless of operands by decoding instructions before locating operand. Unnecessary operations have been reduced by sending operands to some specific operational units, not to all the operational units in ALD. We show that total execution time of a program is minimized by using the Dual Instruction Register(DIR) architecture.