• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1187-1188
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• 2008

An area of research called evolvable hardware has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer. In this paper, we have studied and surveyed a gate-level evolvable hardware chip, by integrating both GA hardware and reconfigurable hardware within a single LSI chip. The chip consists of genetic algorithm(GA) hardware, reconfigurable hardware logic, and the control logic. In this paper, we describe the architecture, functions of the chip.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.281-284
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• 2002

Rijndael algorithm is known to a new private key block cipher which is substitute for DES. Rijndael algorithm is adequate to both hardware and software implementation, so hardware implementation of Rijndael algorithm is applied to high speed data encryption and decryption. This paper describes three implementation methods of Rijndael S-box, which is important factor in performance of Rijndael coprocessor. It shows synthesis results of each S-box implementation in Xilinx FPGA. Tllc lilree S-box implementation methods are implementation using lookup table only, implementation using both lookup table and combinational logic, and implementation using combinational logic only.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.7
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• pp.848-854
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• 1999

In this paper, we designed and implemented a precise pulse motor controller chip that generates the pulse needed to control step motor, DC servo and AC servo motors. This chip generates maximum pulse output rate of 5Mpps and has the quasi-S driving capability and speed and moving distance override capability during driving. We designed this chip with VHDL and executed a logic simulation and synthesis using Synopsys tool. The pre-layout simulation and post-layout simulation was executed by Compass tool. This chip was produced with 100 pins, PQFP package by 0.8${\mu}{\textrm}{m}$ gate array process and implemented by completely digital logic. We developed the test hardware board of performance and the CAMC(Computer Aided Motor Controller) Agent softwate to test the performance of the pulse motor controller chip produced. CAMC Agent enables user to set parameters needed to control motor with easy GUI(Graphic User Interface) environment and to display the output response of motor graphically.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.1033-1036
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• 1993

Most of the today realized fuzzy logic control applications has been designed using different heuristic approaches for synthesis and implemented with conventional programming languages on general purpose microcontrollers. This paper aims to present a new methodology to design a fuzzy controller. The methodology is based on the Cell-to-Cell approach to extract the control law. A set of fuzzy rules is then found by using a FAM (Fuzzy associative memories) approach. The proposed procedure was implemented to control the rotor position of a DC motor.

• Journal of Institute of Control, Robotics and Systems
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• v.7 no.11
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• pp.939-943
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• 2001

PLC(programmable Logic Controller)s essential components of modern automation systems encompassing almost every industry. Ladder Diagrams (LD) have been widely used in the design of such PLC since the LD is suitable for the modeling of the sequential control system. However, the synthesis of LD itself mainly depends on the experience of the industrial engineer, which may results in unstructured or inflexible design. Hence, in this paper, we propose a ladder diagram conversion algorithm which systematically produces LDs for PLCs based on discrete event models to enhance the structured and flexible design mechanism.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.353-356
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• 2002

Due to the increased complexity and size of digital system and the need of the H/W-S/W co-design, C/C++ based system design methodology gains more Interests than ever in EDA field. This paper suggests the methodology in which handshake module corresponding to each basic statement of C is provided of the form of STG(Signal Transition Graph) and then, C statements is synthesized into asynchronous circuit through syntax-oriented translation. The 4-phase handshaking protocol is used for the communications between modules, and the modules are synthesized by the Petrify which is asynchronous logic synthesis CAD tool.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.08a
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• pp.65-68
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• 2000

In this paper, as a compatible software radio transmission system, Digital-Radio conversion system which can directly change the digital signal generated by the logic circuit into radio signal is proposed. By the vector synthesis method, the digital signals can change directly into radio signal. If such a circuit is realized, RF circuit and an antenna can be composed by the simple one device, and the radio is directly controlled and performed by the software processing which is the essence of software radio. This Digital-Radio conversion system of this paper give many number of communication channels being offered by PN code and offer a hardware design flexibility by digitization, therefore it decrease the percentage ratio of hardware of system and give a more flexible function of software basis. In this paper, this proposed Digital-Radio conversion system is called D/R converter, and the principle of this D/R converter, radio signal generation algorithm is explained and the performance characteristics of proposed algorithm is shown in time base by the computer simulation method.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.262-265
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• 2000

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk provides double error detecting and correcting capability. The most complex circuit in the RS decoder is part for solving the error location numbers from error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and Performed logic synthesis using the SYNOPSYS CAD tool. Then, the RS decoder has been implemented with FPGA. The total umber of gate is about 11,000 gates and it operates at 20MHz.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.329-332
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• 2000

This paper proposed resource allocation algorithm for the minimum power consumption of functional unit in high level synthesis process as like DSP which is circuit to give many functional unit. In this paper, the proposed method though high level simulation find switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To used the switching activity find the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.392-395
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• 1999

The state assignment for a finite state machine greatly affects the delay, area, and testabilities of the sequential circuits. In order to minimize the dependencies among state variables, therefore possibly to reduce the length and number of feedback cycles, a new state assignment technique based on m-block partition is introduced in this paper. After the completion of state assignment and logic synthesis, partial scan design is performed to choose minimal number of scan flip-flops. Experiment shows drastic improvement in testabilities while preserving low area and delay overhead.