• 전자공학회논문지C
• /
• 제34C권2호
• /
• pp.1-11
• /
• 1997

We developed a base station modulator ASIC for CDMA digital cellular system. In CDMA digital cellular system, the modulation is performed by convolutional encoding and QPSK with spread spectrum. The function blocks of base station modulator are CRC, convolutional encoder, interleaver pseudo-moise scrambler, power control bit puncturing, walsh cover, QPSK, gain controller, combiner and multiplexer. Each function block was designed by the logic synthesis of VHDL codes. The VHDL code was described at register transfer level and the size of code is about 8,000 lines. The circuit simulation and logic simulation were performed by COMPASS tools. The chip (ES-C2212B CMB) contains 25,205 gates and 3 Kbit SRAM, and its chip size is 5.25 mm * 5,45 mm in 0.8 mm CMOS cell-based design technology. It is packaged in 68 pin PLCC and the power dissipation at 10MHz is 300 mW at 5V. The ASIC has been fully tested and successfully working on the CDMA base station system.

• International Journal of Fuzzy Logic and Intelligent Systems
• /
• 제1권1호
• /
• pp.1-5
• /
• 2001

In this paper, we propose a fuzzy traffic controller that is able to cope with traffic congestion appropriately. In order to consider such situation as loss of green time caused by spillback of upper crossroad, it imports a degree of traffic congestion of upper roads which vehicles on a crossroad are to proceed to. We constructed the equal-partitioned fuzzy traffic controller that uses the membership functions of the same size and shape, and modified the size and shape, and modified the size and shape of its membership functions by the membership function modification algorithm. In experiment, we compared and analyzed the fixed signal controller, the fuzzy traffic controller with the membership of the same size and shape, and the modified fuzzy traffic controller by using the delay time, the proportion of entered vehicles to occurred vehicles and the proportion of passed vehicles to entered vehicles. As a result of experiment, the modified fuzzy controller showed more enhanced performance than others.

• International Journal of Fuzzy Logic and Intelligent Systems
• /
• 제12권4호
• /
• pp.308-318
• /
• 2012

Captions include information which relates to the images. In order to obtain the information in the captions, text extraction methods from images have been developed. However, most existing methods can be applied to captions with a fixed height or stroke width using fixed pixel-size or block-size operators which are derived from morphological supposition. We propose an edge connected components based method that can extract Korean captions that are composed of various sizes and fonts. We analyze the properties of edge connected components embedding captions and build a decision tree which discriminates edge connected components which include captions from ones which do not. The images for the experiment are collected from broadcast programs such as documentaries and news programs which include captions with various heights and fonts. We evaluate our proposed method by comparing the performance of the latent caption area extraction. The experiment shows that the proposed method can efficiently extract various sizes of Korean captions.

• 대한전자공학회논문지
• /
• 제22권1호
• /
• pp.7-13
• /
• 1985

쉽게 시험할 수 특성을 가진 SLA 의 설계에 관해 논하였다. 제안된 SLA는 hardware를 부가함으로써 회로의 상태를 쉽게 조절하고 점검할 수 있게 하였다. 제안된 SLA는 test pattern과 응답이 SLA에 구현된 함수에 관계없고 단지 SLA의 크기에 따라 유일하게 결정되는 매우 짧은 보편적인 test sequence를 갖는다. 여기서 고려된 SLA의 고장은 단일 및 다중 stuck faults, crosspoint faults 및 bridge faults이다. 또한 고장의 위치 판별 및 그 처리에 관해서도 고찰하였다.

• IEIE Transactions on Smart Processing and Computing
• /
• 제2권6호
• /
• pp.367-372
• /
• 2013

Cloud computing technology has been developing at an increasing expansion rate. Today most of firms are using this technology, making improving the quality of service one of the most important issues. To achieve this, the system must operate efficiently with less idle time and without deteriorating the customer satisfaction. This paper focuses on enhancing the efficiency of a conventional Genetic Algorithm (GA) for task scheduling in cloud computing using Fuzzy Logic (FL). This study collected a group of task schedules and assessed the quality of each task schedule with the user expectation. The work iterates the best scheduling order genetic operations to make the optimal task schedule. General GA takes considerable time to find the correct scheduling order when all the fitness function parameters are the same. GA is an intuitive approach for solving problems because it covers all possible aspects of the problem. When this approach is combined with fuzzy logic (FL), it behaves like a human brain as a problem solver from an existing database (Memory). The present scheme compares GA with and without FL. Using FL, the proposed system at a 100, 400 and 1000 sample size*5 gave 70%, 57% and 47% better improvement in the task time compared to GA.

• Progress in Superconductivity
• /
• 제6권1호
• /
• pp.7-12
• /
• 2004

Due to the very fast switching speed of Josephson junctions, superconductive digital circuit has been a very good candidate fur future electronic devices. High-speed and Low-power microprocessor can be developed with Josephson junctions. As a part of an effort to develop superconductive microprocessor, we have designed an RSFQ 4-bit ALU (Arithmetic Logic Unit) in a pipelined structure. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in this work consisted of three DC current driven SFQ switches and a half-adder. We successfully tested the half adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached switches at the input ports to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this setup, 1-bit block of ALU was successfully tested up to 40 GHz. An RSFQ 4-bit ALU was fabricated and tested. The circuit worked at 5 GHz. The circuit size of the 4-bit ALU was 3 mm ${\times}$ 1.5 mm, fitting in a 5 mm ${\times}$ 5 mm chip.

• 전자공학회논문지SC
• /
• 제43권4호
• /
• pp.45-52
• /
• 2006

본 연구에서는 위상잡음과 지터(jitter) 특성을 개선한 $5mm{\times}7mm$ 크기의 적층 세라믹 SMD(surface mounted device)형 VCXO를 개발한다. PECL(positive emitter coupled logic) 칩패키지를 발진수정자에 결선한 VCXO는 그 길이 및 패키지 내부의 패턴 등에 의하여 부유인덕턴스 및 기생 커패시턴스가 발생하고, 전원의 반사 및 잡음 발생으로 출력신호의 진폭 감소 및 신호 손실이 발생하여 발진기 성능을 정상적으로 평가할 수 없다. 이러한 신호 손실 및 진폭감소를 방지하기 위해 지그(Jig) 시스템을 개발하고, 이를 통하여 발진기의 정확한 스펙트럼 분석 및 성능을 평가한다. 동작전원은 3.3 V, 주파수 범위 120-180 MHz 및 Q인수는 5K이다.

• International Journal of Naval Architecture and Ocean Engineering
• /
• 제4권4호
• /
• pp.362-373
• /
• 2012

The ship recycling industry is growing rapidly. It is estimated that the International Maritime Organization's (IMO) decision to phase-out single hull tankers by 2015 will result in hundreds of ships requiring disposal. At present, the ship recycling industry is predominantly based in South Asia. Due to the bad practice of current scrapping procedure, the paper will highlight the harm occurring to health, safety and environment. The efforts of the Marine Environment Protection Committee (MEPC) which led to the signing of the Hong Kong International Convention are also reviewed. The criteria and standards required to reduce the risk and damage to the environment are discussed and a proposed plan for the safe scrapping of ships is then presented. A technological and economic study for the ship recycling in Egypt is carried out as a case study. This includes the ship recycling facility size and layout. The equipment and staff required to operate the facility are also evaluated. A cost analysis is then carried out. This includes site development, human resources, machineries and equipment. A fuzzy logic approach is used to assess the benefits of the ship breaking yard. The use of the fuzzy logic approach is found suitable to make decisions for the ship breaking industry. Based on given constraints, the proposed model has proved capable of assessing the profit and the internal rate of return.

• IEIE Transactions on Smart Processing and Computing
• /
• 제2권4호
• /
• pp.248-254
• /
• 2013

The size and power consumption of digital circuits including the dimming circuit part will increase for high-performance solid state lighting (SSL) systems in the future. This study examined the low-power consumption of adiabatic dynamic CMOS logic (ADCL) due to the principles of adiabatic charging. Furthermore, the designed low-power ADCL digital pulse width modulation (PWM) was optimized for SSL dimming systems. For this purpose, an ADCL digital 3-bit PWM was optimized in two steps. In the first step, the architecture of the ADCL digital 3-bit PWM was miniaturized. In the second step, the clock cut-off circuit was designed and added to the ADCL PWM. As a result, compared to the original configuration, 60 transistors and 15 capacitors of ADCL digital 3-bit PWM were reduced for miniaturization. Moreover, the clock cut-off circuit, which controls wake-up and sleep mode of ADCL D-FFs, was designed. The power consumption of an optimized ADCL digital PWM for all bit patterns decreased by 54 %.

• 융합신호처리학회 학술대회논문집
• /
• 한국신호처리시스템학회 2000년도 추계종합학술대회논문집
• /
• pp.209-212
• /
• 2000

본 논문에서는 AGV(Automatic Guided Vehicle)를 제어하기 위한 hard-wired 제어기를 설계하였고, CPLD(Complex Programmable Logic Device)를 이용하여 구현하였다. 제안된 제어기는 자율주행을 위한 유도장치 제어기, 모터 제어장치, 입출력 sequence 제어기 등을 포함하고 있다. 마이크로프로세서에 의해 구현된 기존방식에 비해 hard-wired 제어방식을 사용하므로 복잡한 프로그램 과정을 줄일 수 있다. 또한 메모리, 조합논리, 순서논리 회로를 쉽게 추가할 수 있어 제품의 개발시간 단축, 제품 크기 축소, 난이도 등에서 발생되는 총 제작비용 등을 감소시킬 수 있다. 제어기는 VHDL을 이용하여 동작적 기술 방법으로 설계되었으며, Altera사의 MAX＋Plus II를 사용하여 합성하였고, EPF10K10LC84-4 디바이스로 구현하여 AGY 모형(Line-tracer)에 적용시켜 동작을 확인하였다.