• Journal of Broadcast Engineering
• /
• v.22 no.5
• /
• pp.618-631
• /
• 2017

In this paper, we propose a modification of fuzzy logic based DASH adaptation algorithm(FDASH) for seamless media service in time-varying network conditions. The proposed algorithm selects more appropriate bit-rate for the next segment by the modification of the Fuzzy Logic Controller(FLC) and reduces the number of video bit-rate changes by applying Segment Bit-rate Filtering Module(SBFM). Also, we apply the Start Mechanism for clients not to watch the low quality videos in the very beginning stage of streaming service and add the Sleeping Mechanism to avoid any buffer overflow expected. Ultimately, we verified by using NS-3 Network Simulator that the proposed method shows better performance compared to FDASH. According to the experimental results, there is no buffer underflow/overflow within the limited buffer size, which is not guaranteed in FDASH on the other hand. Also, we confirmed that mFDASH has almost the same level of average video quality against FDASH and reduces about 50% of number of video bit-rate changes compared to FDASH in Point-to-Point network and Wi-Fi network.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.6
• /
• pp.431-441
• /
• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.11A
• /
• pp.936-944
• /
• 2003

In this paper, we propose an AND/XOR-based technology mapping method for field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into sub-circuits with appropriate number of inputs can achieve excellent implementation efficiency. Specifically, the proposed technology mapping method is based on Davio expansion theorem to decompose a given Boolean circuit. The AND/XOR nature of the proposed method allows it to operate on XOR intensive circuits, such as error detecting/correcting, data encryption/decryption, and arithmetic circuits, efficiently. We conduct experiments using MCNC benchmark circuits. When using the proposed approach, the number of CLBs (configurable logic blocks) is reduced by 67.6% (compared to speed-optimized results) and 57.7% (compared to area-optimized results), total equivalent gate counts are reduced by 65.5 %, maximum combinational path delay is reduced by 56.7 %, and maximum net delay is reduced by 80.5 % compared to conventional methods.

• International Journal of Ocean System Engineering
• /
• v.3 no.1
• /
• pp.16-21
• /
• 2013

This paper presents a design of fuzzy PD depth controller for the autonomous underwater vehicle entitled KAUV-1. The vehicle is shaped like a torpedo with light weight and small size and used for marine exploration and monitoring. The KAUV-1 has a unique ducted propeller located at aft end with yawing actuation acting as a rudder. For depth control, the KAUV-1 uses a mass shifter mechanism to change its center of gravity, consequently, can control pitch angle and depth of the vehicle. A design of classical PD depth controller for the KAUV-1 was presented and analyzed. However, it has inherent drawback of gains, which is their values are fixed. Meanwhile, in different operation modes, vehicle dynamics might have different effects on the behavior of the vehicle. In this reason, control gains need to be appropriately changed according to vehicle operating states for better performance. This paper presents a self-tuning gain for depth controller using the fuzzy logic method which is based on the classical PD controller. The self-tuning gains are outputs of fuzzy logic blocks. The performance of the self-tuning gain controller is simulated using Matlab/Simulink and is compared with that of the classical PD controller.

• Journal of the Korean Electrochemical Society
• /
• v.8 no.4
• /
• pp.149-154
• /
• 2005

Fuel cell performance evaluation logic was developed using G-language (LabVIEW) to measure performance stability. Degree of stability and reliability of performance data were improved with averaged value and standard deviation method. Water injection system was introduced and the performance using this method was comparable to that of conventional humidification method. Water injection system has advantage of lowering operation energy consumption, reducing the number of parts needed in humidification, therefore increasing efficiency of fuel cell system. Fuel cell performance was decreased in case of low temperature operation such as sub freezing condition. Air purge method was tested to reduce the water content in cell fixture before sub freezing condition. The performance degradation due to low temperature operation was minimized by air purge method in medium size cell fixture ($25cm^2$) case.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.10
• /
• pp.1495-1507
• /
• 1993

In this paper, an implementation of RS (Reed-Solomon) code decoder for CDP (Compact Disc Player) using microprogramming method is presented. In this decoding strategy, the equations composed of Newton's identities are used for computing the coefficients of the error locator polynomial and for checking the number of erasures in C2(outer code). Also, in C2 decoding the values of erasures are computed from syndromes and the results of C1(inner code) decoding. We pulled up the error correctability by correcting 4 erasures or less. The decoder contains an arithmetic logic unit over GF(28) for error correcting and a decoding controller with programming ROM, and also microinstructions. Microinstructions are used for an implementation of a decoding algorithm for RS code. As a result, it can be easily modified for upgrade or other applications by changing the programming ROM only. The decoder is implemented by the Logic Level Modeling of Verilog HDL. In the decoder, each microinstruction has 14 bits( = 1 word), and the size of the programming ROM is 360 words. The number of the maximum clock-cycle for decoding both C1 and C2 is 424.

• Journal of the Semiconductor & Display Technology
• /
• v.10 no.3
• /
• pp.1-6
• /
• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.3A
• /
• pp.185-196
• /
• 2009

SCA is proposed in order to operate various wireless systems in the single terminal platforms and uses the CORBA middleware to guarantee the platform-independence for software components. As the reconstruction demand is expanded in the software component to the logic level to many reasons, CORBA has to guarantee the independence of hardware on board. Accordingly. the characteristics depending on hardware board is ed. And the IDL-based interworking interface about the component has to be provided. In this paper, we described about local transport for guaranteeing the independency on the hardware board and the HAO Core for providing a coupling by the CORBA IDL identically with the other component. HAO produced at 2,900 logic cell size in average and provided the performance of the tens times than the software component. Through the use of HAO in the SCA-based development environment, it was naturally expanded to not only the software area but also the FPGA logic.

• Journal of the Institute of Convergence Signal Processing
• /
• v.20 no.3
• /
• pp.118-124
• /
• 2019

Recently, the industrial field has been changed to the smart factory system based on information and communication technology (ICT) in order to improve productivity, quality and customer satisfaction. The most important machine to realize the smart factory is the AGV(automatic guided vehicle) and the adoption of AGV is increasing. Generally, AGV is developed using general purpose PLC(Programmable Logic controller), but the price of AGV is expensive and its volume is large. On the other hand, the industrial field due to space constraints in the workplace is required the low cost AGV which can be minimization, expansion of function, and easily reconfiguration. Therefore, in order to solve these problems, this study is proposed a design method of AGV controller with built-in PLC, and evaluated its performance. In the results of the experimentation, it showed good performance (speed control error = 0.021[m/s], posture control error=2.1[mm]) for the speed and posture control. In this way, when applying the proposed AGV controller in this study to the industrial filed, it is possible to reduce the size and reconfigure at low cost.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.5
• /
• pp.969-976
• /
• 2007

A fuzzy classifier which needs various analyses of features using genetic algorithms is proposed. The fuzzy classifier has a simple structure, which contains a classification part based on fuzzy logic theory and a rule generation part using genetic algorithms. The rule generation part determines optimal fuzzy membership functions and inclusion or exclusion of each feature in fuzzy classification rules. We analyzed recognition rate of a specific object, then added finer features repetitively, if necessary, to the object which has large misclassification rate. And we introduce repetitive analyses method for the minimum size of string and population, and for the improvement of recognition rates. This classifier is applied to two examples of the recognition of iris data and the recognition of Thyroid Gland cancer cells. The fuzzy classifier proposed in this paper has recognition rates of 98.67% for iris data and 98.25% for Thyroid Gland cancer cells.