• Journal of Electrical Engineering and Technology
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• v.4 no.2
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• pp.234-239
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• 2009

In this article we present the simulation results of induction motor speed regulation by direct torque control with a classic PI regulator. The MATLAB Simulink programming environment is used as a simulation tool. The results obtained, using a fuzzy logic, shows the importance of this method in the improvement of the performance of such regulation.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.111-114
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• 2000

Single Electron Transistor Logic (SETL) can be characterized by HSPICE simulation using a SPICE macro model. First, One unit SET is characterized by Monte-carlo simulation and then we fit SPICE macro-modeling equations to its characteristics. Second, using this unit SET, we simulate the transient characteristics of two-input NAND gate in both the static and dynamic logic schemes. The dynamic logic scheme shows more stable operation in terms of logic-swing and on/off current ratio. Also, there is a merit that we can use the SET only as current on-off switch without considering the voltage gain.

• ETRI Journal
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• v.41 no.3
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• pp.383-395
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• 2019

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high-speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high-speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan-in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

• Proceedings of the Korea Society for Simulation Conference
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• 2000.11a
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• pp.241-247
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• 2000

날로 복잡해지고 거대해지는 시스템의 추세를 감안할 때 앞으로 시스템 분야의 주요 구성요소간 상호작용을 분석하여 최적의 시스템 운영방안을 도출하기 위해서는 시뮬레이션 기법의 도입이 필수적이다. Simplus 3D는 분석대상 시스템을 주요 객체 단위로 Model 상에 재구성하여 이들의 움직임과 주체적 의사결정 논리를 자체 서술어를 사용하여 묘사하도록 고안된 범용 그래픽 시뮬레이션 소프트웨어로 사용자가 정의한 Logic을 Procedure 또는 Function화하여 별도의 File에 저장하고 재활용 가능하며, 객체별 Logic Trace가 가능하여 객체 시나리오의 상세분석 및 Logic 디버깅이 용이하다. 또한 대상시스템의 특성에 따라 Macro한 수준의 개략적인 묘사부터 Micro한 수준의 제어 알고리듬에 이르기까지 묘사의 수준이 자유롭고, 시뮬레이션에 주로 사용되는 물류설비 및 Logic을 Module로 제공하며 필요시 Custom Logic을 추가할 수 있다. 분포형태는 일양분포, 지수분포, 정규분포 등 다양한 분포형태를 지원하며 9999개까지의 Random Number Seed 지정이 가능하다. 일반 PC에서도 실행 가능하며 3차원 Animation과 다양한 형태의 Report를 제공함으로써 비전문가나 의사결정자가 각종 대안에 대한 시뮬레이션 결과를 시각적으로 확인하여 쉽게 이해할 수 있도록 하였다. Simplus 3D는 현재까지 생산시스템, 항만 및 교통 등의 분야에 광범위하게 활용되고 있으며, 본 논문에서는 기아자동차 WBS 물류시스템 시뮬레이션 모델과 고속도로 톨게이트 시뮬레이션 모델을 활용사례로 소개하고자 한다.

• The Transactions of the Korea Information Processing Society
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• v.3 no.2
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• pp.315-326
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• 1996

As the complexity of VLSI circuits has increased, a lot of simulation time for verifying their correctness has been required. This paper presents efficient parallelel logic simulation protocols, data structures, algorithms to implement fast logic simulation on SIMD parallel processing computers. The performance results of the presented schemes on CM-2 are given and analyzed.

• Journal of the Korea Society for Simulation
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• v.14 no.3
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• pp.33-42
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• 2005

One of the imminent problems to be solved within wireless sensor network is to balance out energy dissipation among deployed sensor nodes. In this paper, we present a transmission relay method of communications between BS (Base Station) and CHs (Cluster Heads) for balancing the energy consumption and extending the average lifetime of sensor nodes by the fuzzy logic application. The proposed method is designed based on LEACH protocol. The area deployed by sensor nodes is divided into two groups based on distance from BS to the nodes. RCH (Relay Cluster Head) relays transmissions from CH to BS if the CH is in the area far away from BS in order to reduce the energy consumption. RCH decides whether to relay the transmissions based on the threshold distance value that is obtained as a output of fuzzy logic system, Our simulation result shows that the application of fuzzy logic provides the better balancing of energy depletion and prolonged lifetime of the nodes.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.14-19
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• 1997

In this paper, a new fuzzy sliding mode control algorithm is presented for trajectory control of robot manipulators. A fuzzy logic is applied to a sliding mode control algorithm to have the sliding mode gain adjusted continuously through fuzzy logic rules. With this scheme, te stability and the robustness of the proposed fuzzy logic control algorithm are proved and ensured by the sliding mode control law. The fuzzy logic controller requires only a few tuning parameters to adjust. Computer simulation results are given to show that the proposed algorithm can handle uncertain systems with large parameter uncertainties and external disturbances.

• Korean Journal of Optics and Photonics
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• v.17 no.6
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• pp.564-568
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• 2006

Using the cross-gain modulation (XGM) characteristics of semiconductor optical amplifiers (SOAs), multi-functional all-optical logic gates, including XOR, AND, and OR gates are successfully simulated and demonstrated at 10Gbit/s. A VPI component maker^TM simulation tool is used for the simulation of multi-functional all-optical logic gates and the10 Cbit/s input signal is made by a mode-locked fiber ring laser. A multi-quantum well (MQW) SOA is used for the simulation and demonstration of the all-optical logic system. Our suggested system is composed of three MQW SOAs, SOA-1 and SOA-2 for XOR logic operation and SOA-2 and SOA-3 for AND logic operation. By the addition of two output signals XOR and AND, all-optical OR logic can be obtained.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.446-449
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• 2004

We developed a dynamic logic architecture which resulted better leakage current, lower power consumption and less area compared to the conventional dynamic logic structures. We demonstrated the advantage from HSPICE simulation and test chip design has been completed.