• Title/Summary/Keyword: Logic Simulation

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Comparative Study of PI, Fuzzy and Fuzzy tuned PI Controllers for Single-Phase AC-DC Three-Level Converter

  • Gnanavadivel, J;Senthil Kumar, N;Yogalakshmi, P
    • Journal of Electrical Engineering and Technology
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    • v.12 no.1
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    • pp.78-90
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    • 2017
  • This paper presents the design of closed loop controllers operating a single-phase AC-DC three-level converter for improving power quality at AC mains. Closed loop inhibits outer voltage controller and inner current controller. Simulations of three level converter with three different voltage and current controller combinations such as PI-Hysteresis, Fuzzy-Hysteresis and Fuzzy tuned PI-Hysteresis are carried out in MATLAB/Simulink. Performance parameters such as input power factor and source current total harmonic distortion (THD) are considered for comparison of the three controller combinations. The fuzzy-tuned PI voltage controller with hysteresis current controller combination provides a better result, with a source-current THD of 0.93% and unity power factor without any source side filter for the three level converter. For load variations of 25% to 100%, a THD of less than 5% is obtained with a maximum value of only 1.67%. Finally, the fuzzy-tuned PI voltage with hysteresis controller combination is implemented in a Xilinx Spartan-6 XC6SLX25 FPGA board for experimental validation of power quality enhancement. A prototype 100 W, 0-24-48 V as output converter is considered for the testing of controller performance. A source-current THD of 1.351% is obtained in the experimental study with a power factor near unity. For load variations of 25% to 100%, the THD is found to be less than 5%, with a maximum value of only 2.698% in the experimental setup which matches with the simulation results.

Autonomous Stationkeeping System for Geostationary Satellite (정지위성 자동위치유지 시스템에 관한 연구)

  • Park, Bong-Kyu;Tahk, Min-Jea;Bang, Hyo-Choong
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.32 no.10
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    • pp.67-76
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    • 2004
  • This paper improves existing 'fly-the-wire' based autonomous station-keeping system, suitable for geostationary satellite and introduces results of computer simulations conducted to verify the algorithm. The on-board stationkeeping system receives pseudo-range signals from two ground equipments located with long baseline, determines the orbit error in realtime and generates orbit control commands. To reduce fuel consumption, this paper proposes an on-board orbit control logic using modified fly-the-wire method. The modified fly-the-wire method de-couples error components into two dynamic modes, harmonic and linear motion. The harmonic error components are removed by applying output commands produced by feedback controller, and the linear motions are controlled by the correction ${\Delta}V\;s$ added to reference maneuvers. The reference maneuvers are generated through the ground based computer simulation and embedded or uploaded into the on-board computer with time tags. Finally, the performance of the proposed algorithm is verified through a series of computer simulations.

(A Dual Type PFD for High Speed PLL) (고속 PLL을 위한 이중구조 PFD)

  • 조정환;정정화
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.39 no.1
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    • pp.16-21
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    • 2002
  • In this paper, a dual type PFD(Phase Frequency Detector) for high speed PLL to improve output characteristics using TSPC(True Single Phase Clocking) circuit is proposed. The conventional 3-state PFD has problems with large dead-zone and long delay time. Therefore, it is not applicable to high-speed PLL(Phase-Locked Loop). A dynamic PFD with dynamic CMOS logic circuit is proposed to improve these problems. But, it has the disadvantage of jitter noise due to the variation of the duty cycle. In order to solve the problems of previous PFD, the proposed PFD improves not only the dead zone and duty cycle but also jitter noise and response characteristics by the TSPC circuit and dual structured PFD circuit. The PFD is consists of a P-PFD(Positive edge triggered PFD) and a N-PFD(Negative edge triggered PFD) and improves response characteristics to increase PFD gain. The Hspice simulation is performed to evaluate the performance of proposed PFD. From the experimental results, it has the better dead zone, duty cycle and response characteristics than conventional PFDs.

Design of a High-speed Decision Feedback Equalizer using the Constant-Modulus Algorithm (CMA 알고리즘을 이용한 고속 DFE 등화기 설계)

  • Jeon, Yeong-Seop;;Kim, Gyeong-Ho
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.39 no.4
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    • pp.173-179
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    • 2002
  • This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. The DFE structure has better channel adaptive performance and lower BER than the transversal structure. The proposed equalizer can be used for 16/64 QAM modems. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL filter. The proposed equalizer shows low BER in multipath fading channel. We have performed models. From the simulation results, we employ a 12 tap feedback filter and a 8 tap feedforward logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5$\mu\textrm{m}$ standard cell library (STD80) and verified function and timing simulations. The total number of gates is about 130,000.

Low Voltage Swing BUS Driver and Interface Analysis for Low Power Consumption (전력소모 감소를 위한 저 전압 BUS 구동과 인터페이스 분석)

  • Lee Ho-Seok;Kim Lee-Sup
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.7
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    • pp.10-16
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    • 1999
  • This paper describes a low voltage swing bus driver using FCSR(Feedback Control Swing voltage Reduction) which can control bus swing voltage within a few hundred of mV. It is proposed to reduce power consumption in On-chip interface, especially for MDL(Merged DRAM Logic) architecture wihich has wide and large capacitance bus. FCSR operates on differential signal dual-line bus and on precharged bus with block controlling fuction. We modeled driver and bus to scale driver size automatically when bus environment is variant. We also modeled coupling capacitance noise(crosstalk) of neighborhood lines which operate on odd mode with parallel current source to analysis crosstalk effect in the victim-line according as voltage transition in the aggressor-line and environment in the victim-line. We built a test chip which was designed to swing 600mV in bus, shows 70Mhz operation at 3.3V, using Hyundai 0.8um CMOS technology. FCSR operate with 250Mhz at 3.3V by Hspice simulation.

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On Motion Planning for Human-Following of Mobile Robot in a Predictable Intelligent Space

  • Jin, Tae-Seok;Hashimoto, Hideki
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.4 no.1
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    • pp.101-110
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    • 2004
  • The robots that will be needed in the near future are human-friendly robots that are able to coexist with humans and support humans effectively. To realize this, humans and robots need to be in close proximity to each other as much as possible. Moreover, it is necessary for their interactions to occur naturally. It is desirable for a robot to carry out human following, as one of the human-affinitive movements. The human-following robot requires several techniques: the recognition of the moving objects, the feature extraction and visual tracking, and the trajectory generation for following a human stably. In this research, a predictable intelligent space is used in order to achieve these goals. An intelligent space is a 3-D environment in which many sensors and intelligent devices are distributed. Mobile robots exist in this space as physical agents providing humans with services. A mobile robot is controlled to follow a walking human using distributed intelligent sensors as stably and precisely as possible. The moving objects is assumed to be a point-object and projected onto an image plane to form a geometrical constraint equation that provides position data of the object based on the kinematics of the intelligent space. Uncertainties in the position estimation caused by the point-object assumption are compensated using the Kalman filter. To generate the shortest time trajectory to follow the walking human, the linear and angular velocities are estimated and utilized. The computer simulation and experimental results of estimating and following of the walking human with the mobile robot are presented.

Fuzzy Controller for Nonlinear Systems Using Optimal Pole Placement (최적 극점 배치를 이용한 비선형 시스템의 퍼지 제어기)

  • 이남수
    • Journal of the Korean Institute of Intelligent Systems
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    • v.10 no.2
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    • pp.152-160
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    • 2000
  • This paper addresses the analysis and design of fuzzy-model-based controller for nonlinear systems using extended PDC and optimal pole-placement schemes. In the design procedure, we represent the nonlinear system using a Takagi-Sugeno fkzy model and formulate the controller rules by using the extended parallel distributed compensator (EPDC) and construct an overall fuzzy logic controller by blending all local state feedback controllers with an optimal pole-placement scheme. Unlike the commonly used parallel distributed compensation technique, by blending a newly extended parallel distributed compensator and the optimal poleplacement schemes, we can design not only a local stable k z y controller but also an overall stable fuzzy controller to perform the tacking control objective. Furthermore, a stability analysis is carried out not only for the fuzzy model but also for a real nonlinear system. Finally. the effectiveness and feasibility of the proposed fizzy model-based controller design method has been shown through a simulation example.

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A New Approach to Solve the TSP using an Improved Genetic Algorithm

  • Gao, Qian;Cho, Young-Im;Xi, Su Mei
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.11 no.4
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    • pp.217-222
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    • 2011
  • Genetic algorithms are one of the most important methods used to solve the Traveling Salesman Problem. Therefore, many researchers have tried to improve the Genetic Algorithm by using different methods and operations in order to find the optimal solution within reasonable time. This paper intends to find a new approach that adopts an improved genetic algorithm to solve the Traveling Salesman Problem, and compare with the well known heuristic method, namely, Kohonen Self-Organizing Map by using different data sets of symmetric TSP from TSPLIB. In order to improve the search process for the optimal solution, the proposed approach consists of three strategies: two separate tour segments sets, the improved crossover operator, and the improved mutation operator. The two separate tour segments sets are construction heuristic which produces tour of the first generation with low cost. The improved crossover operator finds the candidate fine tour segments in parents and preserves them for descendants. The mutation operator is an operator which can optimize a chromosome with mutation successfully by altering the mutation probability dynamically. The two improved operators can be used to avoid the premature convergence. Simulation experiments are executed to investigate the quality of the solution and convergence speed by using a representative set of test problems taken from TSPLIB. The results of a comparison between the new approach using the improved genetic algorithm and the Kohonen Self-Organizing Map show that the new approach yields better results for problems up to 200 cities.

Design and FPGA Implementation of a High-Speed RSA Algorithm for Digital Signature (디지털 서명을 위한 고속 RSA 암호 시스템의 설계 및 FPGA 구현)

  • 강민섭;김동욱
    • The KIPS Transactions:PartC
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    • v.8C no.1
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    • pp.32-40
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    • 2001
  • In this paper, we propose a high-speed modular multiplication algorithm which revises conventional Montgomery's algorithm. A hardware architecture is also presented to implement 1024-bit RSA cryptosystem for digital signature based on the proposed algorithm. Each iteration in our approach requires only one addition operation for two n-bit integers, while that in Montgomery's requires two addition operations for three n-bit integers. The system which is modelled in VHDL(VHSIC Hardware Description Language) is simulated in functionally through the use of $Synopsys^{TM}$ tools on a Axil-320 workstation, where Altera 10K libraries are used for logic synthesis. For FPGA implementation, timing simulation is also performed through the use of Altera MAX + PLUS II. Experimental results show that the proposed RSA cryptosystem has distinctive features that not only computation speed is faster but also hardware area is drastically reduced compared to conventional approach.

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Performance Investigation of Semi-Active Control Logic to Minimize a Pointing Performance Degradation of On-Board Payload by Chattering Effects (Chattering에 의한 위성 탑재체 지향성능저하 최소화를 위한 반능동제어기법 성능분석)

  • Oh, Hyun-Ung;Choi, Young-Jun
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.38 no.9
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    • pp.882-889
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    • 2010
  • Semi-active vibration control is one of the attractive control methods for space application due to its robustness as passive damping system and much higher damping performance than passive system. However, a chattering induced by the sudden variation of damping force at the time of On-Off switching of semi-active control device degrades pointing performance of the on-board payload. In this paper, to enhance the pointing performance of the on-board payload, we proposed a semi-active vibration isolation with a strategy for attenuating chattering effect. Numerical simulation results using simplified analysis model indicated that the proposed semi-active control strategy produced much better isolation performance than the conventional Bang-Bang control semi-active control laws derived from skyhook and LQ theories.