• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.533-536
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• 2005

MAP algorithm is known for optimal decoding algorithm of Turbo codes, but it has very large computational complexity and delay. Generally log-MAP algorithm is used in order to overcome the defect. In this paper we propose modified scheme of the state metric calculation block which can improve the computation speed in log-MAP decoder and simple linear offset unit without using LUT. The simulation results show that the operation speed of the proposed scheme is improved as compared with that of the past scheme.

• The KIPS Transactions:PartA
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• v.12A no.3 s.93
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• pp.205-214
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• 2005

Flash memory is at high speed used as storage of personal information utilities, ubiquitous computing environments, mobile phones, electronic goods, etc. This is because flash memory has the characteristics of low electronic power, non-volatile storage, high performance, physical stability, portability, and so on. However, differently from hard disks, it has a weak point that overwrites on already written block of flash memory is impossible to be done. In order to make an overwrite possible, an erase operation on the written block should be performed before the overwrite, which lowers the performance of flash memory highly. In order to solve this problem the flash memory controller maintains a system software module called the flash translation layer(FTL). Of many proposed FTL schemes, the log block buffer scheme is best known so far. This scheme uses a small number of log blocks of flash memory as a write buffer, which reduces the number of erase operations by overwrites, leading to good performance. However, this scheme shows a weakness of low page usability of log blocks. In this paper, we propose an enhanced log block buffer scheme, FAST(Full Associative Sector Translation), which improves the page usability of each log block by fully associating sectors to be written by overwrites to the entire log blocks. We also show that our FAST scheme outperforms the log block buffer scheme.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.4
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• pp.767-783
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• 2013

This paper aims at designing a selective demodulation scheme based on Log-likelihood Ratio threshold (SDLT) instead of the conventional adaptive demodulation (ADM) scheme, by using rateless codes. The major difference is that the Log-likelihood ratio (LLR) threshold is identified as a key factor to control the demodulation rate, while the ADM uses decision region set (DRS) to adjust the bit rate. In the 16-QAM SDLT scheme, we deduce the decision regions over an additive white Gaussian channel, corresponding to the variation of LLR threshold and channel states. We also derived the equations to calculate demodulation rate and bit error rate (BER), which could be proven by simulation results. We present an adaptation strategy for SDLT, and compare it with ADM and adaptive modulation (AM). The simulation results show that our scheme not only significantly outperforms the ADM in terms of BER, but also achieves a performance as good as the AM scheme. Moreover, the proposed scheme can support much more rate patterns over a wide range of channel states.

• ETRI Journal
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• v.33 no.6
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• pp.957-960
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• 2011

We present a fair and efficient solution for selfish readers with the Nash bargaining solution (NBS) to mitigate the effects of RFID frequency interference. We compare the NBS with a solution derived by the max log-sum scheme that maximizes total utility and show that for selfish and rational readers, the NBS brings success in bargaining on resource allocation between readers unlike the max log-sum scheme, although the NBS has less total payoff compared to the max log-sum scheme.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.2
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• pp.50-57
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• 1998

In this paper, we propoe a log N-stage ATM concentator. ATM concentrator is used in the ATM access network to concentrate the traffic offered at UNI, so that high utilization of the newtork rewources is achieved. The concetrator may be used as a construction block in the design of ATM switch. We define abasic element, named equalizer, and decribe its function and theory to construct an efficient concentrator using the element. In addition, a control scheme to enhance the concentrator to a superconcentrator is presented, which enables the concentration to start from an arbitrary output. This scheme makes it possible to construct an efficient ditributior or a barrel shifter which are often used in ATM switch and other application. The proposed concentrator has a low hardware complexity of O(N log N), thus it is economical to implement. Also, the time complexity of proposed concentrator for determining the rouging is O(N log N), which is faster than that of the existing ones.

• Journal of Digital Contents Society
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• v.14 no.2
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• pp.215-222
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• 2013

NAND flash memory-based Solid State Drives (SSD) have lots of merits compared to traditional hard disk drives (HDD). However, random write in SSD is still far slower than sequential read/write and random read. There are two independent approaches to resolve this problem: 1) using part of the flash memory blocks as log blocks, and 2) using internal write buffer (DRAM or Non-Volatile RAM) in SSD. While log blocks are managed by the Flash Translation Layer (FTL), write buffer management has been treated separately from FTL. Write buffer management schemes did not use the exact status of log blocks and log block management schemes in FTL did not consider the behavior of write buffer management scheme. In this paper, we first show that log blocks and write buffer have a tight relationship to each other, which necessitates integrated management of both of them. Since log blocks also can be viewed as another type of write buffer, we can manage both of them as an integrated write buffer. Then we provide three design criteria for the integrated write buffer management scheme which can be very useful to SSD firmware designers.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.2
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• pp.90-102
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• 2010

Flash memory has been widely used as an important storage device for consumer electronics. For the flash memory-based storage systems, FTL (Flash Translation Layer) is used to handle the mapping between a logical page address and a physical page address. Especially, log buffer-based FTLs provide a good performance with small-sized mapping information. In designing the log buffer-based FTL, one important factor is to determine the mapping structure between data blocks and log blocks, called associativity. While previous works use static associativity fixed at the design time, we propose a new log block mapping scheme which adjusts associativity based on the run-time workload. Our proposed scheme improves the I/O performance about 5~16% compared to the static scheme by adjusting the associativity to provide the best performance.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.4
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• pp.85-91
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• 2019

In this paper, we propose a new logging and recovery scheme that is suited for the high-performance transaction processing system base on flash memory storage. The proposed scheme is designed by considering flash's I/O characteristic of asymmetric costs between page update/read operations. That is, we substitute the costly update operation with writing and real-time usage of snapshot log, which is for the page-level physical redo. From this, we can avoid costly rewriting of a dirty page when it is evicted form a buffering pool. while supporting efficient revery procedure. The proposed scheme would be not lucrative in the case of HDD-based system. However, the proposed scheme offers the performance advance sush as a reduced number of updates and the fast system recovery time, in the case of flash storage such as SSD (solid state drive). Because the proposed scheme can easily be applied to existing systems by saving our snapshot records and ordinary log records together, our scheme can be used for improving the performance of upcoming SSD-based database systems through a tiny modification to existing REDO algorithms.

• The Journal of the Korea Contents Association
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• v.10 no.1
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• pp.68-77
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• 2010

In this paper, we propose a new log buffer management scheme considering the accessibility of the data. Our proposed scheme evaluates the worth of the merge of log blocks. It conducts the merge operations between infrequently updated data and the data blocks and postpones as much as possible the merge operations between frequently updated data and the data blocks. As a result, the proposed method prevents the unnecessary merge operations, reduces the number of the erase operations, and improves the utilization of the flash memory storage. In order to show the superiority of the proposed scheme, we compare it with BAST and FAST. It is shown through performance evaluation that the proposed method achieves about 25% and 65% performance improvements over BAST and FAST on average in terms of the number of the erase operations.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.1
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• pp.414-430
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• 2016

Verifier-local revocation (VLR) seems to be the most flexible revocation approaches for any group signature scheme, because it just only requires the verifiers to possess some up-to-date revocation information, but not the signers. Langlois et al. (PKC 2014) proposed the first VLR group signature based on lattice assumptions in the random oracle model. Their scheme has at least Õ(n²) ⋅ log N bit group public key and Õ(n) ⋅ log N bit signature, respectively. Here, n is the security parameter and N is the maximum number of group members. In this paper, we present a simpler lattice-based VLR group signature, which is more efficient by a O(log N) factor in both the group public key and the signature size. The security of our VLR group signature can be reduced to the hardness of learning with errors (LWE) and small integer solution (SIS) in the random oracle model.