• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.476-487
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• 2007

Flash memory offers attractive features, such as non-volatile, shock resistance, fast access, and low power consumption for data storage. However, it has one main drawback of requiring an erase before updating the contents. Furthermore, flash memory can only be erased limited number of times. To overcome limitations, flash memory needs a software layer called flash translation layer (FTL). The basic function of FTL is to translate the logical address from the file system like file allocation table (FAT) to the physical address in flash memory. In this paper, a new FTL algorithm called an efficient and advanced space-management technique (EAST) is proposed. EAST improves the performance by optimizing the number of log blocks, by applying the state transition, and by using reallocation blocks. The results of experiments show that EAST outperforms FAST, which is an enhanced log block scheme, particularly when the usage of flash memory is not full.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.5
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• pp.74-82
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• 2011

SSD has a limitation of number of erase/write cycles and does not allow in-place update unlike the hard disk because SSD is composed of an array of NAND flash memory. Thus, FTL is used to effectively manage SSD of having different characteristics from traditional disk. FTL has page, block, log-block mapping method. Among then, when log-block mapping method such as BAST and FAST is used, the performance of SSD is degraded because frequent merge operations cause lots of pages to be copied and deleted. This paper proposes a data allocation and replacement method based on access frequency by allocating PRAM as checking area of access frequency, log blocks, storing region of hot data in SSD. The proposed method can enhance the performance and lifetime of SSD by storing cold data to flash memory and storing log blocks and frequently accessed data to PRAM and then reducing merge and erase operations. Besides, a data replacement method is used to increase utilization of PRAM which has limitation of capacity. The experimental results show that the ratio of erase operations of the proposed method is 46%, 38% smaller than those of BAST and FAST and the write performance of the proposed method is 34%, 19% higher than those of BAST and FAST, and the read performance of the proposed method is 5%, 3% higher than those of BAST and FAST, respectively.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.499-502
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• 2001

Fractal image coding suffers from the long search time of domain pool although it provides many properties including the high compression ratio. We find that the normalized variance of a block is independent of contrast, brightness. Using this observation, we introduce a self similar block searching method employing the d-dimensional nearest neighbor searching. This method takes Ο(log/N) time for searching the self similar domain blocks for each range block where N is the number of domain blocks. PSNR (Peak Signal Noise Ratio) of this method is similar to that of the full search method that requires Ο(N) time for each range block. Moreover, the image quality of this method is independent of the number of edges in the image.

• Journal of KIISE
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• v.41 no.12
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• pp.1026-1034
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• 2014

Recently, flash storages devices have become popular. Log-structured file systems (LFS) are suitable for flash storages since these can provide high write performance by only generating sequential writes to the flash device. However, LFS should perform garbage collections (GC) in order to reclaim obsolete space. Recently, a slack space recycling (SSR) technique was proposed to reduce the GC overhead. However, since SSR generates random writes, write performance can be negatively impacted if the random write performance is significantly lower than sequential write performance of the target device. This paper proposes a partial garbage collection technique that copies only a part of valid blocks in a victim segment in order to increase the size of the contiguous invalid space to be used by SSR. The experiments performed in this study show that the write performance in an SD card improves significantly as a result of the partial GC technique.

• Communications for Statistical Applications and Methods
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• v.17 no.1
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• pp.27-37
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• 2010

This article concerns the forecasting in binomial AR(p) models which is proposed by Wei$\ss$ (2009b) for time series of binomial counts. Our method extends to binomial AR(p) models a recent result by Jung and Tremayne (2006) for integer-valued autoregressive model of second order, INAR(2), with simple Poisson innovations. Forecasts are produced by conditional median which gives 'coherent' forecasts, and we estimate the forecast distributions of future values of binomial AR(p) models by means of a Monte Carlo method allowing for parameter uncertainty. Model parameters are estimated by the method of moments and estimated standard errors are calculated by means of block of block bootstrap. The method is fitted to log data set used in Wei$\ss$ (2009b).

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.157-160
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• 2003

Recently, several steganographic algorithms for two-color binary images have been proposed. In this paper, we propose a steganographic algorithm which embeds a secret message into bitmap images and palette-based images. To embed a message, the suggested algorithm divides a bitmap image into bit-plane images from LSB-plane to MSB-plane for each pixel, and considers each bit-plane image as a binary one. The algorithm splits each bit-plane image into m$\times$n blocks. and embeds a r-bit(r=[log$_2$(mn+1]-1) message into the block. And our schemes embed a message to every bit-plane from LSB to MSB to maximize the amount of embedded message and to minimize the degradation. The schemes change at most two pixels in each block. Therefore, the maximal color changes of the new algorithm are much smaller than other bit-plane embedding schemes' such as the substantial substitution schemes.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.278-281
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• 2009

In this paper, we propose a fast partial distortion algorithm using normalized dithering matching scan to get uniform distribution of partial distortion which can reduce only unnecessary computation significantly. Our algorithm is based on normalized dithering order matching scan and calibration of threshold error using LOG value for each sub-block continuously for efficient elimination of unlike candidate blocks while keeping the same prediction quality compared with the full search algorithm. Our algorithm reduces about 60% of computations for block matching error compared with conventional PDE (partial distortion elimination) algorithm without any prediction quality, and our algorithm will be useful to real-time video coding applications using MPEG-4 AVC or MPEG-2.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.145-149
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• 2011

Recently, as the design of a system gets larger and more complex, functional verification method based on system-level becomes more important. The verification of a functional block mainly uses BFM(bus functional model). The larger the burden on functional verification is, the more the importance of configuring a proper verification environment increases rapidly. SystemVerilog unifies hardware design languages and verification languages in the form of extensions to the Veri log HDL. The processing of design description, function simulation and verification using same language has many advantages in system development. In this paper, we design DUT that is composed of AMBA bus and function blocks using SystemVerilog and verify the function of DUT in verification environment using layered testbench. Adaptive FIR filter and Booth's multiplier are chosen as function blocks. We confirm that verification environment can be reused through a minor adaptation of interface to verify functions of other DUT.

• Journal of KIISE
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• v.42 no.4
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• pp.442-450
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• 2015

This paper proposes a method for reducing false conflicts in signature-based eager hardware transactional memory (HTM). The method tracks the information on all cache blocks that are accessed by a transaction. If the information provides evidence that there are no conflicts for a given transactional request from another core, the method prevents the occurrence of a false conflict by forcing the HTM to ignore the decision based on the signature. The method is very effective in reducing false conflicts and the associated unnecessary transaction stalls and aborts, and can be used to improve the performance of the multicore processor that implements the signature-based eager HTM. When running the STAMP benchmark on a 16-core processor that implements the LogTM-SE, the increased speed (decrease in execution time) achieved with the use of the method is 20.6% on average.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8A
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• pp.725-732
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• 2002

Block-wise MAP (Maximum A posteriori) decoding algorithm for turbo-codes requires less memory than Log-MAP decoding algorithm. The ER (Bit Error Rate) performance of previous block-wise MAP decoding algorithm depend on the block length and training length. To maximize hardware utilization and perform successive decoding, the block length is set to be equal to the training length in previous MAP decoding algorithms. Simulation result on the BER performance shows that the EBR performance can be maintained with shorter blocks when training length is sufficient. This paper proposes an architecture for area efficient block-wise MAP decoder. The proposed architecture employs the decoding schema for reducing memory by using the training length, which in N times larger than block length. To efficiently handle the proposed schema, a pipelined architecture is proposed. Simulation results show that memory usage can be reduced by 30%~45% in the proposed architecture without degrading the BER performance.