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Data allocation and Replacement Method based on The Access Frequency for Improving The Performance of SSD  

Yang, Yu-Seok (Department of Electronic Engineering, Inha University)
Kim, Deok-Hwan (Department of Electronic Engineering, Inha University)
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Abstract
SSD has a limitation of number of erase/write cycles and does not allow in-place update unlike the hard disk because SSD is composed of an array of NAND flash memory. Thus, FTL is used to effectively manage SSD of having different characteristics from traditional disk. FTL has page, block, log-block mapping method. Among then, when log-block mapping method such as BAST and FAST is used, the performance of SSD is degraded because frequent merge operations cause lots of pages to be copied and deleted. This paper proposes a data allocation and replacement method based on access frequency by allocating PRAM as checking area of access frequency, log blocks, storing region of hot data in SSD. The proposed method can enhance the performance and lifetime of SSD by storing cold data to flash memory and storing log blocks and frequently accessed data to PRAM and then reducing merge and erase operations. Besides, a data replacement method is used to increase utilization of PRAM which has limitation of capacity. The experimental results show that the ratio of erase operations of the proposed method is 46%, 38% smaller than those of BAST and FAST and the write performance of the proposed method is 34%, 19% higher than those of BAST and FAST, and the read performance of the proposed method is 5%, 3% higher than those of BAST and FAST, respectively.
Keywords
SSD; Flash memory; FTL; PRAM; Data allocation;
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1 J. Kim, J.M. Kim, S.H. Noh, S. Min, and Y. Cho. "A Space-Efficient Flash Translation Layer for Compactflash Systems", IEEE Transactions on Consumer Electronics, 48(2), pp.366-375, 2002.   DOI   ScienceOn
2 S.-W. Lee, D.-J. Park, T.-S. Chung, D.H. Lee, S. Park, and H.-J. Song, "A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation", ACM Transactions on Embedded Computing Systems, 6(3), Article 18, 2007.
3 S. Im and D. Shin. Storage architecture and software support for SLC/MLC combined flash memory. In Proceedings of the 2009 ACM symposium on Applied Computing, pp.1664-1669, 2009.
4 G.H. Koh and et el., 2004. "PRAM Process Technology", in Proceeding of the IEEE International Conference on Integrated Circuit Design and Technology, 2004.
5 Kinam Kim and G.H. Koh, 2004. "Future Memory Technology including Emerging New Memories", in Proceedings of 24th International Conference on Microelectronics, NIS, Serbia and Montenegro, May, 2004.
6 양유석, 송재석, 김덕환, "데이터 할당과 선반입 기법을 이용한 SSD 스토리지의 성능 향상", 대한전자공학회 추계학술대회 논문집, pp.599-600, 2010년 11월.
7 Y. Joo, et al. "Energy-and endurance-away design of phase change memory caches", In Proceedings of DATE, 2010.
8 J. K. Kim et al., "A PRAM and NAND flash hybrid architecture for high-performance embedded storage subsystems," in Proceedings of 2008, pp. 31-40, 2008.
9 G. Sun, Y. Joo, Y. Chen, D. Niu, Y. Xie, Y. Chen, and H. Li. A hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. In Proceedings of HPCA'10, Jan 2010.
10 Intel Corporation, "Understanding the Flash Translation Layer Specification," http://developer.intel.com, 1998.
11 A. Birrel, M. Isard, C. Thancker, and T. Wobber, 2007. "A design for High-Performance Flash Disks". ACM SIGOPS Operating Systems Review, 41(2), April 2007.
12 N. Agrawal and et al. "Design Tradeoffs for SSD Performance", in Proceedings of USENIX, 2008.
13 A. Ban. "Flash file system. United States Patent", No. 5,404,485, April 1995.
14 Y. Park et al., "PFFS: a scalable flash memory file system for the hybrid architecture of phase-change RAM and NAND flash," in Proceedings of ACM SAC 2008, pp. 1498-1503, 2008.