• 대한전자공학회논문지
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• 제13권5호
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• pp.24-29
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• 1976

Phase locked AM신호 검파방식에서는 위상고정회로를 사용하여 입력신호로부터 반송신호를 분리 재생시킨다. 입력잡음은 백색 Gaussian잡음이고, 전려제어발진기의 자유발진주파수와 입력반송신호주파수가 같다는 가정하에 위상고정회로의 동작특성을 해석하고, 본 검파방식의 신호대 잡음비를 정량적으로 고찰하였다. Phase locked AM신호 검파방식은 종래의 검파방식에 비해서 잡음의 영향을 적게 받게됨을 본 해석에서 알 수 있다. In the phase locked AM signal detection, phase locked loop is used to extract a synchronous carrier from an input AM signal. Under the assumption that input noise is white Gaussian and free-running frequency of voltage controlled oscillator is the same that of an input carrier, operational behaviours of phase locked loop is analyzed and signal to noise ratio of the detection is derived quentitatively. The results show that the phase locked AM signal detection method offers a higher degree of noise mmunity than conventional AM signal detections.

• Journal of Electrical Engineering and Technology
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• 제11권6호
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• pp.1707-1713
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• 2016

This paper proposes a dc error compensation algorithm using dq-synchronous coordinate transform digital phase-locked-loop in single-phase grid-connected converters. The dc errors are caused by analog to digital conversion and grid voltage during measurement. If the dc offset error is included in the phase-locked-loop system, it can cause distortion in the grid angle estimation with phase-locked-loop. Accordingly, recent study has dealt with the integral technique using the synchronous reference frame phase-locked-loop method. However, dynamic response is slow because it requires to monitor one period of grid voltage. In this paper, the dc offset error compensation algorithm of the improved response characteristic is proposed by using the synchronous reference frame phase-locked-loop. The simulation and the experimental results are presented to demonstrate the effectiveness of the proposed dc offset error compensation algorithm.

• Journal of information and communication convergence engineering
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• 제2권2호
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• pp.102-105
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• 2004

A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 um Standard CMOS process and it operates at 5 GHz frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권3호
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• pp.131-140
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• 2005

Fault-tolerant gait generation of a hexapod robot with crab walking is proposed. The considered fault is a locked joint failure, which prevents a joint of a leg from moving and makes it locked in a known position. Due to the reduced workspace of a failed leg, fault-tolerant crab walking has a limitation in the range of heading direction. In this paper, an accessible range of the crab angle is derived for a given configuration of the failed leg and, based on the principles of fault-tolerant gait planning, periodic crab gaits are proposed in which a hexapod robot realizes crab walking after a locked joint failure, having a reasonable stride length and stability margin. The proposed crab walking is then applied to path planning on uneven terrain with positive obstacles. i.e., protruded obstacles which legged robots cannot cross over but have to take a roundabout route to avoid. The robot trajectory should be generated such that the crab angle does not exceed the restricted range caused by a locked joint failure.

• Journal of electromagnetic engineering and science
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• 제17권3호
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• pp.138-146
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• 2017

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

• Journal of Trauma and Injury
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• 제25권1호
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• pp.7-16
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• 2012

Purpose: Cervical dislocations with locked facets account for more than 50% of all cervical injuries. Thus, investigating a suitable management of cervical locked facets is important. This study examined factors of close reduction failure in traumatically locked facets of the subaxial cervical spine patients to determine suitable surgical management. Methods: We retrospectively analyzed of the case histories of 28 patients with unilateral/bilateral cervical locked facets from Nov. 2004 to Dec. 2010. Based on MRI evaluation of disc status at the injury level, we found unilateral dislocations in 9 cases, and bilateral dislocations in 19 cases, The patients were investigated for neurologic recovery, closed reduction rate, factors of the close reduction barrier, fusion rate and period, spinal alignment, and complications. Results: The closed reduction failed in 23(82%) patients. Disc herniation was an obstacle to closed reduction (p=0.015) and was more frequent in cases involving a unilateral dislocation (p=0.041). The pedicle or facet fracture was another factor, although some patients showed aggravation of neurologic symptoms, most patients had improved by the last follow up. The kyphotic angle were statistically significant (p=0.043). Sixs patient underwent anterior decompression/fusion, and 15 patients underwent circumferential fusion, and 7 patients underwent posterior fusion. All patients were fused at 3 months after surgery. The complications were 1 case of CSF leakage and 1 case of esphageal fistula, 1 case of infection. Conclusion: We recommend closed reduction be performed as soon as possible after injury to maximize the potential for neurological recovery. Patients fot whom closed reduction of the cervical locked facets have a higher incidence of anatomic obstacles to reduction, including facet fractures and disc herniation. Immediate direct open anterior reduction or circumferential fixation/fusion of locked cervical facets is recommended as a treatment of choice for traumatic locked cervical facet patients after closed reduction failure.

• Journal of Semiconductor Engineering
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• 제1권1호
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• pp.1-12
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• 2020

Handling precise timing in high-speed transceivers has always been a primary design target to achieve better performance. Many different approaches have been tried, and one of those is utilizing the beneficial nature of injection locking. Though the phenomenon was not intended for building integrated circuits at first, its coupling effect between neighboring oscillators has been utilized deliberately. Consequently, the dynamics of the injection-locked oscillator (ILO) have been explored, starting from R. Adler. As many aspects of the ILO were revealed, further studies followed to utilize the technique in practice, suggesting alternatives to the conventional frequency syntheses, which tend to be complicated and expensive. In this review, the historical analysis techniques from R. Adler are studied for better comprehension with proper notation of the variables, resulting in numerical results. In addition, how the timing jitter or phase noise in the ILO is attenuated from noise sources is presented in contrast to the clock generators based on the phase-locked loop (PLL). Although the ILO is very promising with higher cost effectiveness and better noise immunity than other schemes, unless correctly controlled or tuned, the promises above might not be realized. In order to present the favorable conditions, several strategies have been explored in diverse applications like frequency multiplication, data recovery, frequency division, clock distribution, etc. This paper reviews those research results for clock multiplication and data recovery in detail with their advantages and disadvantages they are referring to. Through this review, the readers will hopefully grasp the overall insight of the ILO, as well as its practical issues, in order to incorporate it on silicon successfully.

• 대한전기학회논문지:시스템및제어부문D
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• 제52권12호
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• pp.689-695
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• 2003

Fault-tolerance is an important design criterion for robotic systems operating in hazardous or remote environments. This paper addresses the issue of tolerating a locked joint failure in gait planning for hexapod walking machines which have symmetric structures and legs in the form of an articulated arm with three revolute joints. A locked joint failure is one for which a joint cannot move and is locked in place. If a failed joint is locked, the workspace of the resulting leg is constrained, but hexapod walking machines have the ability to continue static walking. A strategy of fault-tolerant tripod gait is proposed and, as a specific form, a periodic tripod gait is presented in which hexapod walking machines have the maximum stride length after a locked failure. The adjustment procedure from a normal gait to the proposed fault-tolerant gait is shown to demonstrate the applicability of the proposed scheme.

• 제어로봇시스템학회논문지
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• 제9권11호
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• pp.943-951
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• 2003

A strategy for fault-tolerant gaits of autonomous legged robots is proposed. A legged robot is considered to be fault tolerant with respect to a given failure if it is guaranteed to be capable of walking maintaining its static stability after the occurrence of the failure. The failure concerned in this paper is a locked joint failure for which a joint in a leg cannot move and is locked in place. If a failed joint is locked, the workspace of the resulting leg is constrained, but legged robots have fault tolerance capability to continue static walking. An algorithm for generating fault-tolerant gaits is described and, especially, periodic gaits are presented for forward walking of a hexapod robot with a locked joint failure. The leg sequence and the formula of the stride length are analytically driven based on gait study and robot kinematics. The transition procedure from a normal gait to the proposed fault-tolerant gait is shown to demonstrate the applicability of the proposed scheme.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 춘계학술대회 논문집 디스플레이 광소자분야
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• pp.146-149
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• 2004

We have studied a liquid crystal (LC) mode (named locked super homeotropic (LSH)) in which the LCs aligned homeotropically are locked by surrounding walls such as cubic, hexagonal and cylinder. In the device, the vertically aligned LCs tilt down symmetrically around the center of the cell when a voltage is applied and thus it exhibits wide viewing angle. The structure of this LSH mode is suitable for large-sized display panels. since the LCs are locked in micro domains the LCs do not flow to the bottom of the panel by gravity. This mode is applicable to achieve high performance TFT-LCD TV because of high performance characteristics such as high contrast, high brightness, wide-viewing angle.