• 제목/요약/키워드: Local memory

검색결과 361건 처리시간 0.036초

A Study on the PWM Controller of DC-AC Inverter using the Multiprocessor System (다중프로세서 방식을 사용한 직류-교류변환기의 펄스폭변조제어에 관한 연구)

  • 이윤종;이성백
    • The Journal of Korean Institute of Communications and Information Sciences
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    • 제12권5호
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    • pp.505-518
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    • 1987
  • In this paper, the 2-level and 3-level types of PWM technique have been analyzed, and a multiprocessor has been designed as controller for these two types of PWM inverters. Designed multiprocessor employing a hierarchical structure of a SUPERVISORY PROCESSOR which interconnects three LOCAL PROCESSOR through a common memory technique has showed as elaborate digital control characteristic. Using this multiprocessor configuration the system could gain a great degree of freedom in change of software. Also software was simpler than a single processor configuration.

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A hybrid CSS and PSO algorithm for optimal design of structures

  • Kaveh, A.;Talatahari, S.
    • Structural Engineering and Mechanics
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    • 제42권6호
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    • pp.783-797
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    • 2012
  • A new hybrid meta-heuristic optimization algorithm is presented for design of structures. The algorithm is based on the concepts of the charged system search (CSS) and the particle swarm optimization (PSO) algorithms. The CSS is inspired by the Coulomb and Gauss's laws of electrostatics in physics, the governing laws of motion from the Newtonian mechanics, and the PSO is based on the swarm intelligence and utilizes the information of the best fitness historically achieved by the particles (local best) and by the best among all the particles (global best). In the new hybrid algorithm, each agent is affected by local and global best positions stored in the charged memory considering the governing laws of electrical physics. Three different types of structures are optimized as the numerical examples with the new algorithm. Comparison of the results of the hybrid algorithm with those of other meta-heuristic algorithms proves the robustness of the new algorithm.

Action Recognition with deep network features and dimension reduction

  • Li, Lijun;Dai, Shuling
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제13권2호
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    • pp.832-854
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    • 2019
  • Action recognition has been studied in computer vision field for years. We present an effective approach to recognize actions using a dimension reduction method, which is applied as a crucial step to reduce the dimensionality of feature descriptors after extracting features. We propose to use sparse matrix and randomized kd-tree to modify it and then propose modified Local Fisher Discriminant Analysis (mLFDA) method which greatly reduces the required memory and accelerate the standard Local Fisher Discriminant Analysis. For feature encoding, we propose a useful encoding method called mix encoding which combines Fisher vector encoding and locality-constrained linear coding to get the final video representations. In order to add more meaningful features to the process of action recognition, the convolutional neural network is utilized and combined with mix encoding to produce the deep network feature. Experimental results show that our algorithm is a competitive method on KTH dataset, HMDB51 dataset and UCF101 dataset when combining all these methods.

Sinusoidal Map Jumping Gravity Search Algorithm Based on Asynchronous Learning

  • Zhou, Xinxin;Zhu, Guangwei
    • Journal of Information Processing Systems
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    • 제18권3호
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    • pp.332-343
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    • 2022
  • To address the problems of the gravitational search algorithm (GSA) in which the population is prone to converge prematurely and fall into the local solution when solving the single-objective optimization problem, a sine map jumping gravity search algorithm based on asynchronous learning is proposed. First, a learning mechanism is introduced into the GSA. The agents keep learning from the excellent agents of the population while they are evolving, thus maintaining the memory and sharing of evolution information, addressing the algorithm's shortcoming in evolution that particle information depends on the current position information only, improving the diversity of the population, and avoiding premature convergence. Second, the sine function is used to map the change of the particle velocity into the position probability to improve the convergence accuracy. Third, the Levy flight strategy is introduced to prevent particles from falling into the local optimization. Finally, the proposed algorithm and other intelligent algorithms are simulated on 18 benchmark functions. The simulation results show that the proposed algorithm achieved improved the better performance.

A Study on Authentication and Authorization on Entity in Grid (Grid 환경에서 엔티티 인증과 권한부여에 관한 연구)

  • Kug, Joung-Ook;Lee, Jae-Kwang
    • The KIPS Transactions:PartC
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    • 제10C권3호
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    • pp.273-280
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    • 2003
  • When an existing user authorization systems in Grid access many user to local system and subject DN (Distinguished Name) in a user-proxy authenticate and ID in local system is one-to-one mapping, they have difficulties in ID management, memory resource management and resource management. At this, a variety of subject DN is shared of one local ID in an existing Grid. But this faces many difficulties in applying all requirements for many Grid users. Thus, we suppose user authorization system based on a certificate not them based on ID in this paper. That is, we add user's access level to extension field in a certificate, and make a supposed authorization system decide access limitation level on resources instead of an existing ID mapping methods.

LOCAL AND GLOBAL EXISTENCE AND BLOW-UP OF SOLUTIONS TO A POLYTROPIC FILTRATION SYSTEM WITH NONLINEAR MEMORY AND NONLINEAR BOUNDARY CONDITIONS

  • Wang, Jian;Su, Meng-Long;Fang, Zhong-Bo
    • Bulletin of the Korean Mathematical Society
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    • 제50권1호
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    • pp.37-56
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    • 2013
  • This paper deals with the behavior of positive solutions to the following nonlocal polytropic filtration system $$\{u_t=(\mid(u^{m_1})_x{\mid}^{{p_1}^{-1}}(u^{m_1})_x)_x+u^{l_{11}}{{\int_0}^a}v^{l_{12}}({\xi},t)d{\xi},\;(x,t)\;in\;[0,a]{\times}(0,T),\\{v_t=(\mid(v^{m_2})_x{\mid}^{{p_2}^{-1}}(v^{m_2})_x)_x+v^{l_{22}}{{\int_0}^a}u^{l_{21}}({\xi},t)d{\xi},\;(x,t)\;in\;[0,a]{\times}(0,T)}$$ with nonlinear boundary conditions $u_x{\mid}{_{x=0}}=0$, $u_x{\mid}{_{x=a}}=u^{q_{11}}u^{q_{12}}{\mid}{_{x=a}}$, $v_x{\mid}{_{x=0}}=0$, $v_x|{_{x=a}}=u^{q21}v^{q22}|{_{x=a}}$ and the initial data ($u_0$, $v_0$), where $m_1$, $m_2{\geq}1$, $p_1$, $p_2$ > 1, $l_{11}$, $l_{12}$, $l_{21}$, $l_{22}$, $q_{11}$, $q_{12}$, $q_{21}$, $q_{22}$ > 0. Under appropriate hypotheses, the authors establish local theory of the solutions by a regularization method and prove that the solution either exists globally or blows up in finite time by using a comparison principle.

VLSI Design for Motion Estimation Based on Bit-plane Matching (비트 플레인 정합에 의한 움직임 추정기의 VLSI 설계)

  • Go, Yeong-Gi;O, Hyeong-Cheol;Go, Seong-Je
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • 제38권5호
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    • pp.509-517
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    • 2001
  • Full-search algorithm requires large amount of computation which causes time delay or very complex hardware architecture for real time implementation. In this paper, we propose a fast motion estimator based on bit-plane matching, which reduce the computational complexity and the hardware cost. In the proposed motion estimator, the conventional motion estimation algorithms are applied to the binary images directly extracted from the video sequence. Furthermore, in the proposed VLSI motion estimator, we employ a Pair of processing cores that calculate the motion vector continuously By controlling the data flow in a systolic fashion using the internal shift registers in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and adopt lower-cost fabrication technology. We modeled and tested the proposed motion estimator in VHDL, and then synthesized the whole system which has been integrated in a 0.6-$\mu$m triple-metal CMOS chip of size 8.15 X 10.84$\textrm{mm}^2$.

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Cache Coherency Schemes for Database Sharing Systems with Primary Copy Authority (주사본 권한을 지원하는 공유 데이터베이스 시스템을 위한 캐쉬 일관성 기법)

  • Kim, Shin-Hee;Cho, Haeng-Rae;Kim, Byeong-Uk
    • The Transactions of the Korea Information Processing Society
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    • 제5권6호
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    • pp.1390-1403
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    • 1998
  • Database sharing system (DSS) refers to a system for high performance transaction processing. In DSS, the processing nodes are locally coupled via a high speed network and share a common database at the disk level. Each node has a local memory, a separate copy of operating system, and a DB'\fS. To reduce the number of disk accesses, the node caches database pages in its local memory buffer. However, since multiple nodes may be simultaneously cached a page, cache consistency must be cnsured so that every node can always access the'latest version of pages. In this paper, we propose efficient cache consistency schemes in DSS, where the database is logically partitioned using primary copy authority to reduce locking overhead, The proposed schemes can improve performance by reducing the disk access overhead and the message overhead due to maintaining cache consistency, Furthermore, they can show good performance when database workloads are varied dynamically.

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Design and Performance Analysis of A TMS320C67x-based Parallel Signal Processing System (TMS320C67x 기반 병렬신호처리시스템의 설계와 성능분석)

  • Moon, Byung-Pyo;Park, Joon-Seok;Jeon, Chang-Ho;Park, Sung-Joo;Lee, Dong-Ho;Han, Ki-Taek
    • The Transactions of the Korea Information Processing Society
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    • 제7권1호
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    • pp.65-73
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    • 2000
  • This paper deals with a design and performance analysis of a parallel signal processing system based on TMS320C67x. With an emphasis on the board-level design of the processor unit four models are proposed with different memory configurations and internal bus schemes. Several approaches to parallel processing of 2D FFT are also presented to be used for performance analysis. The performance of four board models are estimated and compared in terms of the time spent for local memory access, inter-processor communication, and inter-board communication. The results of performance analysis show that, when performance and implementation complexity are taken into account, the model with both local and shared memories is the most desirable.

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A Study on H-CNN Based Pedestrian Detection Using LGP-FL and Hippocampal Structure (LGP-FL과 해마 구조를 이용한 H-CNN 기반 보행자 검출에 대한 연구)

  • Park, Su-Bin;Kang, Dae-Seong
    • The Journal of Korean Institute of Information Technology
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    • 제16권12호
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    • pp.75-83
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    • 2018
  • Recently, autonomous vehicles have been actively studied. Pedestrian detection and recognition technology is important in autonomous vehicles. Pedestrian detection using CNN(Convolutional Neural Netwrok), which is mainly used recently, generally shows good performance, but there is a performance degradation depending on the environment of the image. In this paper, we propose a pedestrian detection system applying long-term memory structure of hippocampal neural network based on CNN network with LGP-FL (Local Gradient Pattern-Feature Layer) added. First, change the input image to a size of $227{\times}227$. Then, the feature is extracted through a total of 5 layers of convolution layer. In the process, LGP-FL adds the LGP feature pattern and stores the high-frequency pattern in the long-term memory. In the detection process, it is possible to detect the pedestrian more accurately by detecting using the LGP feature pattern information robust to brightness and color change. A comparison of the existing methods and the proposed method confirmed the increase of detection rate of about 1~4%.