• Title/Summary/Keyword: Link Matching

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Efficient Construction of Generalized Suffix Arrays by Merging Suffix Arrays (써픽스 배열 합병을 이용한 일반화된 써픽스 배열의 효율적인 구축 알고리즘)

  • Jeon, Jeong-Eun;Park, Heejin;Kim, Dong-Kyue
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.6
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    • pp.268-278
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    • 2005
  • We consider constructing the generalized suffix way of strings A and B when the suffix arrays of A and B are given, j.e., merging two suffix arrays of A and B. There are efficient algorithms to merge some special suffix arrays such as the odd array and the even array. However, for the general case that A and B are arbitrary strings, no efficient merging algorithms have been developed. Thus, one had to construct the generalized suffix arrays of A and B by constructing the suffix array of A$\#$B$\$$ from scratch, even though the suffix ways of A and B are given. In this paper, we Present efficient merging algorithms for the suffix arrays of two arbitrary strings A and B drawn from constant and integer alphabets. The experimental results show that merging two suffix ways of A and B are about 5 times faster than constructing the suffix way of A$\#$B$\$$ from scratch for constant alphabets. Our algorithms include searching all suffixes of string B in the suffix array of A. To do this, we use suffix links in suffix ways and we developed efficient algorithms for computing the suffix links. Efficient computation of suffix links is another contribution of this paper because it can be used to solve other problems occurred in bioinformatics that should search all suffixes of a given string in the suffix array of another string such as computing matching statistics, finding longest common substrings, and so on. The experimental results show that our methods for computing suffix links is about 3-4 times faster than the previous fastest methods.

Semantic Search System using Ontology-based Inference (온톨로지기반 추론을 이용한 시맨틱 검색 시스템)

  • Ha Sang-Bum;Park Yong-Tack
    • Journal of KIISE:Software and Applications
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    • v.32 no.3
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    • pp.202-214
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    • 2005
  • The semantic web is the web paradigm that represents not general link of documents but semantics and relation of document. In addition it enables software agents to understand semantics of documents. We propose a semantic search based on inference with ontologies, which has the following characteristics. First, our search engine enables retrieval using explicit ontologies to reason though a search keyword is different from that of documents. Second, although the concept of two ontologies does not match exactly, can be found out similar results from a rule based translator and ontological reasoning. Third, our approach enables search engine to increase accuracy and precision by using explicit ontologies to reason about meanings of documents rather than guessing meanings of documents just by keyword. Fourth, domain ontology enables users to use more detailed queries based on ontology-based automated query generator that has search area and accuracy similar to NLP. Fifth, it enables agents to do automated search not only documents with keyword but also user-preferable information and knowledge from ontologies. It can perform search more accurately than current retrieval systems which use query to databases or keyword matching. We demonstrate our system, which use ontologies and inference based on explicit ontologies, can perform better than keyword matching approach .

High-Efficiency CMOS Power Amplifier using Low-Loss PCB Balun with Second Harmonic Impedance Matching (2차 고조파 정합 네트워크를 포함하는 저손실 PCB 발룬을 이용한 고효율 CMOS 전력증폭기)

  • Kim, Hyungyu;Lim, Wonseob;Kang, Hyunuk;Lee, Wooseok;Oh, Sungjae;Oh, Hansik;Yang, Youngoo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.30 no.2
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    • pp.104-110
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    • 2019
  • In this paper, a complementary metal oxide semiconductor(CMOS) power amplifier(PA) integrated circuit operating in the 900 MHz band for long-term evolution(LTE) communication systems is presented. The output matching network based on a transformer was implemented on a printed circuit board for low loss. Simultaneously, to achieve high efficiency of the PA, the second harmonic impedances are controlled. The CMOS PA was fabricated using a $0.18{\mu}m$ CMOS process and measured using an LTE uplink signal with a bandwidth of 10 MHz and peak to average power ratio of 7.2 dB for verification. The implemented CMOS PA module exhibits a power gain of 24.4 dB, power-added efficiency of 34.2%, and an adjacent channel leakage ratio of -30.1 dBc at an average output power level of 24.3 dBm.

A Study on Algorithm and Operation Technique for Dynamic Hard Shoulder Running System on Freeway (고속도로 동적 갓길차로제 알고리즘과 운영기법 연구)

  • Nam Sik Moon;Eon kyo Shin;Ju hyun Kim
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.23 no.4
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    • pp.16-36
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    • 2024
  • This study, developed a dynamic hard shoulder running(HSR) algorithm that includes ending speed and minimum operation time in addition to the starting speed for HSR, and presented an operation plan. The first stage of the algorithm was red, which means vehicles are prohibited from HSR. The second stage is red/amber, in which drivers are notified of HSR, and operators are given time to check whether there is any obstacle to HSR. Stage 3 is green, which vehicles are permitted for HSR. Stage 4 is amber, in which a signal is given to drivers that the end of HSR is imminent. In addition, a minimum time is applied to green and red, but if congestion is severe, red is terminated early to prevent congestion from worsening. The upstream and downstream traffic flow is managed stably through main line ramp metering and lane number matching. The operating standard speed reflects the characteristics of vehicles and drivers, and based on simulation results, 7090 was selected as the optimal operating standard speed considering traffic flow and safety aspects. Therefore it is desirable to apply the travel time divided by the minimum speed of the HSR link as the minimum operating time in order to ensure continuity of traffic flow

A Study on the Optimal Aggregation Interval for Travel Time Estimation on the Rural Arterial Interrupted Traffic flow (지방부 간선도로 단속류 통행시간 추정을 위한 적정 집락간격 결정에 관한 연구)

  • Lim Houng-Seak;Lee Seung-Hwan;Lee Hyun-Jae
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.3 no.2 s.5
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    • pp.129-140
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    • 2004
  • In this paper, we conduct the research about optimal aggregation interval of travel time data on interrupted traffic flow and verify the reliability of AVI collected data by using car plate matching method in RTMS for systematic collection and analysis of link travel time data on interrupted traffic flow rural arterial. We perform Kolmosorov-Smirnov test on AVT collected sample data and on entire population data, and conclude that the sample data does not represent pure random sampling and hence includes sample collection error. We suggest that additional review is necessary to investigate the effectiveness of AVI collected sample data as link representative data. We also develop statistical model by applying two estimation techniques namely point estimation and interval estimation for calculating optimal aggregation interval. We have implemented our model and determine that point estimate is preferable over interval estimate for exactly selecting and deciding optimal aggregation interval. Our final conclusion is that 5-minute aggregation interval is optimal to estimate travel time in RTMS, as is currently being used our investigation is based on AVI data collected from Yang-ji to Yong-in $42^{nd}$ National road.

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A Novel Adaptive Routing Algorithm for Delay-Sensitive Service in Multihop LEO Satellite Network

  • Liu, Liang;Zhang, Tao;Lu, Yong
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.10 no.8
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    • pp.3551-3567
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    • 2016
  • The Low Earth Orbit satellite network has the unique characteristics of the non-uniform and time-variant traffic load distribution, which often causes severe link congestion and thus results in poor performance for delay-sensitive flows, especially when the network is heavily loaded. To solve this problem, a novel adaptive routing algorithm, referred to as the delay-oriented adaptive routing algorithm (DOAR), is proposed. Different from current reactive schemes, DOAR employs Destination-Sequenced Distance-Vector (DSDV) routing algorithm, which is a proactive scheme. DSDV is extended to a multipath QoS version to generate alternative routes in active with real-time delay metric, which leads to two significant advantages. First, the flows can be timely and accurately detected for route adjustment. Second, it enables fast, flexible, and optimized QoS matching between the alternative routes and adjustment requiring flows and meanwhile avoids delay growth caused by increased hop number and diffused congestion range. In addition, a retrospective route adjustment requesting scheme is designed in DOAR to enlarge the alternative routes set in the severe congestion state in a large area. Simulation result suggests that DOAR performs better than typical adaptive routing algorithms in terms of the throughput and the delay in a variety of traffic intensity.

An Adaptive FEC Algorithm for Mobile Wireless Networks (이동 무선 네트워크의 전송 성능 향상을 위한 적응적 FEC 알고리즘)

  • Ahn, Jong-Suk;John Heidmann
    • The KIPS Transactions:PartC
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    • v.9C no.4
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    • pp.563-572
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    • 2002
  • Wireless mobile networks tend to drop a large portion of packets due to propagation errors rather than congestion. To Improve reliability over noisy wireless channels, wireless networks can employ forward error correction (FEC) techniques. Static FEC algorithms, however, can degrade the performance by poorly matching their overhead to the degree of the underlying channel error, especially when the channel path loss rate fluctuates widely. This paper investigates the benefits of an adaptable FEC mechanism for wireless networks with severe packet loss by analytical analysis or measurements over a real wireless network called sensor network. We show that our adaptive FEC named FECA (FEC-level Adaptation) technique improves the performance by dynamically tuning FEC strength to the current amount of wireless channel loss. We quantify these benefits through a hybrid simulation integrating packet-level simulation with bit-level details and validate that FECA keeps selecting the appropriate FEC-level for a constantly changing wireless channel.

Performance Evaluation and Analysis of a VHF-UHF Blade Antenna (VHF-UHF 대역 블레이드 안테나의 성능 평가 및 분석)

  • Go, Jooseoc;Byun, Gangil;Kim, Kichul;Ju, Jeungmin;Choo, Hosung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.10
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    • pp.951-957
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    • 2013
  • In this paper, we propose a performance evaluation process of aircraft blade antennas. The process consists of various sub-processes that should be considered for a stable communication link with the base station. The process begins with the settlement of the ground shape and size to evaluate the impedance matching characteristics of a stand-alone antenna. Next, the main communications area of the antenna is determined by considering a flight scenario, and then the minimum gain requirements of the antenna are derived in the operating frequency band. Finally, the proposed evaluation process is applied for a commercial aircraft blade antenna. The results demonstrate that the proposed process is suitable to be adopted for the evaluation of aircraft blade antennas.

A 5.8GHz SiGe Down-Conversion Mixer with On-Chip Active Batons for DSRC Receiver (DSRC수신기를 위한 능동발룬 내장형 5.8GHz SiGe 하향믹서 설계 및 제작)

  • 이상흥;이자열;이승윤;박찬우;강진영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.4A
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    • pp.415-422
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    • 2004
  • DSRC provides high speed radio link between Road Side Equipment and On-Board Equipment within the narrow communication area. In this paper, a 5.8 GHz down-conversion mixer for DSRC communication system was designed and fabricated using 0.8 ${\mu}{\textrm}{m}$ SiGe HBT process technology and RF/LO matching circuits, RF/LO input balun circuits, and If output balun circuit were all integrated on chip. The chip size of fabricated mixer was 1.9 mm${\times}$1.3 mm and the measured performance was 7.5 ㏈ conversion gain, -2.5 ㏈m input IP3, 46 ㏈ LO to RF isolation, 56 ㏈ LO to IF isolation, current consumption of 21 mA for 3.0 V supply voltage.

A 5.8 GHz SiGe Up-Conversion Mixer with On-Chip Active Baluns for DSRC Transmitter (DSRC 송신기를 위한 능동발룬 내장형 5.8 GHz SiGe 상향믹서 설계 및 제작)

  • Lee Sang heung;Lee Ja yol;Kim Sang hoon;Bae Hyun cheol;Kang Jin yeong;Kim Bo woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.4A
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    • pp.350-357
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    • 2005
  • DSRC provides high speed radio link between Road Side Equipment and On-Board Equipment within the narrow communication area. In this paper, a 5.8 GHz up-conversion mixer for DSRC communication system was designed and fabricated using 0.8 m SiGe HBT process technology and IF/LO/RF matching circuits, IF/LO input balun circuits, and RP output balun circuit were all integrated on chip. The chip size of fabricated mixer was $2.7mm\times1.6mm$ and the measured performance was 3.5 dB conversion gain, -12.5 dBm output IP3, 42 dB LO to If isolation, 38 dB LO to RF isolation, current consumption of 29 mA for 3.0 V supply voltage.