• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 춘계학술대회 논문집 반도체재료
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• pp.34-37
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• 2001

As the integrated circuit device shrinks to smaller dimensions, chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the inter-metal dielectrics (IMD) layer gets thinner, micro-scratches are becoming as major defects. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. To prevent agglomerated slurry particle from inflow, we installed 0.5${\mu}m$ POU (point of use) filter, which is depth-type filter and has 80% filtering efficiency for the $1.0{\mu}m$ size particle. In this paper, we studied the relationship between defect generation and pad count to understand the exact efficiency of the slurry filtration, and to find out the appropriate pad usage. Our preliminary results showed that it is impossible to prevent defect-causing particles perfectly through the depth-type filter. Thus, we suggest that it is necessary to optimize the flow rate of slurry to overcome depth type filters weak-point, and to install the high spray of de-ionized Water (DIW) with high pressure.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 A
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• pp.438-439
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• 2006

Porcelain insulators have generally been used in Korea to insulate a transmission line from the tower, and a highly polymerized compound polymer insulator which has superior stain proof characteristics, has also been used widely. Currently, a worker rides on the suspension insulator string for installation on towers and conductors but in case of polymer insulators, this will pollute and scratch the housing result in durability reduction by deterioration and corona. This study developed a high strength aluminum compound metal lauder designed to work on polymer insulators without riding, and a clamp type connecting device and safety gear for easy installation on the tower and conductor. These polymer insulator work device can be used for 154kV and 345kV polymer insulators through a strength and load test to secure safety. This paper presents field usage.

• 소성∙가공
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• 제13권4호
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• pp.326-333
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• 2004

The nanoprobe based on lithography, mainly represented by SPM based technologies, has been recognized as a potential application to fabricate the surface nanosctructures because of its operational versatility and simplicity. However, nanoprobe based on lithography itself is not suitable for mass production because it is time a consuming method and not economical for commercial applications. One solution is to fabricate a mold that will be used for mass production processes such as nanoimprint, PDMS casting, and others. The objective of this study is to fabricate the silicon stamper for PDMS casting process by a mastless fabrication technique using the combination of nano/micro machining by Nanoindenter XP and KOH wet etching. Effect of the Berkovich tip alignment on the deformation was investigated. Grooves were machined on a silicon surface, which has native oxide on it, by constant load scratch (CLS), and they were etched in KOH solutions to investigate chemical characteristics of the machined silicon surface. After the etching process, the convex structures was made because of the etch mask effect of the mechanically affected layer generated by nanoscratch. On the basis of this fact, some line patterns with convex structures were fabricated. Achieved groove and convex structures were used as a stamper for PDMS casting process.

• 한국인터넷방송통신학회논문지
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• 제16권3호
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• pp.123-128
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• 2016

이차 전지 생산 공정에서 발생되는 전극 표면의 결함을 검사하는 비전 시스템을 연구 개발한다. 전극 표면 검사 비전 시스템은 제어 및 광학계의 하드웨어 설계 부분과 비전 검사용 소프트웨어 알고리즘 개발로 크게 두 부분으로 구성된다. 하드웨어는 시스템 구성, 광학계의 설계, 조명부, 제어부로 나누어지며 소프트웨어는 결함 검출 알고리즘을 개발 구현한다. 이 시스템을 통해서 전극 공정의 자동 결함 검출을 통해서 품질 향상과 가격 경쟁을 목표로 한다. 제안된 결함 검출 알고리즘을 이용하여 검사한 결과 전극의 반점, 라인, 맨홀, 이물, 스크래치, 분화구 불량에 대해서 높은 신뢰성을 보인다.

• 대한기계학회논문집
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• 제8권3호
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• pp.195-200
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• 1984

본 연구에서는 SUS 304강의 상온하의 평골재 표면에 발생. 성장하는 미소표면 피로균열의 거동을 파괴역학적 관점과 수법으로 정량적으로 조사하려는 연구의 일환 이다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 제5회 영호남 학술대회 논문집
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• pp.12-14
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP). process was required for the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. It is well known that the presence of hard and larger size particles in the CMP slurries increases the defect density and surface roughness of the polished wafers. In this paper, we have studied. aging effect the of CMP slurry as a function of particle size. We prepared and compared the self-developed silica slurry by adding of abrasives before and after annealing. As our preliminary experiment results, we could be obtained the relatively stable slurry characteristics comparable to original silica slurry in the slurry aging effect.

• 한국전기전자재료학회논문지
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• 제14권9호
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• pp.707-713
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• 2001

As the integrated circuit device shrinks to smaller dimensions, chemical mechanical polishing (CMP) process was requirdfo the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the IMD layer gest thinner, micro-scratches are becoming as major defects. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. To prevent agglomerated slurry particle from inflow, we installed 0.5${\mu}{\textrm}{m}$ point of use (POU) filter, which is depth-type filter and has 80% filtering efficiency for the 1.0${\mu}{\textrm}{m}$ size particle. In this paper, we studied the relationship between defect generation and polished wafer counts to understand the exact efficiency fo the slurry filteration, and to find out the appropriate pad usage. Our experimental results showed that it sis impossible to prevent defect-causing particles perfectly through the depth-type filter. Thus, we suggest that it is necessary to optimize the slurry flow rate, and to install the high spray bar of de-ionized water (DIW) with high pressure, to overcome the weak-point of depth type filter.

• 한국전기전자재료학회논문지
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• 제17권2호
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• pp.138-143
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• 2004

CMP (Chemical Mechanical Polishing) technology for global planarization of multilevel interconnection structure has been widely studied for the next generation devices. Among the consumables for CMP process, especially, slurry and their chemical compositions play a very important role in the removal rates and within-wafer non-uniformity (WIWNU) for global planarization ability of CMP process. However, CMP slurries contain abrasive particles exceeding 1 ${\mu}{\textrm}{m}$ size, which can cause micro-scratch on the wafer surface after CMP process. Such a large size particle in these slurries may be caused by particle agglomeration in slurry supply-line. In this work, to investigate the effects of agglomeration on the performance of oxide CMP slurry, we have studied an aging effect of silica slurry as a function of particle size distribution and aging time during one month. We Prepared and compared the self-developed silica slurry by adding of alumina powders. Also, we have investigated the oxide CMP characteristics. As an experimental result, we could be obtained the relatively stable slurry characteristics comparable to aging effect of original silica slurry. Consequently, we can expect the saving of high-cost slurry.

• 한국정보통신학회논문지
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• 제10권2호
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• pp.308-314
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• 2006

수 마이크로 단위로 계측되는 반도체 COG의 검사 정밀도를 높이기 위해서 라인스캔 카메라가 이용된다. 여러 가지 불량 요인 중 이물질 검출은 COG 패턴이 미세하고 복잡하기 때문에 불량 자동 검사 단계에서 가장 어려운 기술이었다. 본 논문에서는 매칭 속도를 높이기 위하여 2단계 영역분할 템플릿 매칭 방법을 제안하였다. 아울러 수 마이크로 단위의 이물짙 검출을 위하여 그라디언트 마스크와 AND 연산을 이용한 새로운 방법을 제안하였다. 제안된 2단계 템플릿 매칭을 사용한 방법은 기존의 상관 계수 이용법 에 비해 0.3-0.4초 매칭 속도를 향상시켰다. 그리고 제안된 마스크 적용 이물질 검출방법은 기존 마스크를 이용하지 않은 방법에 비해 불량 검출률을 $5-8\%$ 향상시켰다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
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• pp.37-40
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. It is well known that the presence of hard and larger size particles in the CMP slurries increases the defect density and surface roughness of the polished wafers. In this paper, we have studied aging effect the of CMP slurry as a function of particle size. We prepared and compared the self-developed silica slurry by adding of abrasives before and after annealing. As our preliminary experiment results, we could be obtained the relatively stable slurry characteristics comparable to original silica slurry in the slurry aging effect.