• Macromolecular Research
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• v.16 no.7
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• pp.644-650
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• 2008

This study examined the effect of nanoclays on the shape memory behavior of polyurethane (PU) in fibrous form. A cation was introduced into the PU molecules to disperse the organo-nanoclay (MMT) into poly($\varepsilon$-caprolactone) (PCL)-based PU (PCL-PU). The MMT/PCL-PU nanocomposites were then spun into fibers through melt-processing. The shape memory performance of the spun fibers was examined using a variety of thermo-mechanical tests including a new method to determine the transition temperature of shape memory polymers. The MMTs showed an improved the fixity strain rate of the MMT /PCL- PU fibers but a slight decrease in their recovery strain rate. This was explained by the limited movement of PU molecules due to the presence of nanoclays. The shape memory performance of the MMT/PCL-PU fibers was not enhanced significantly by the nanoclays. However, their recovery power was improved significantly up to a strain of approximately 50%.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.1
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• pp.69-77
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• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.

• Electronics and Telecommunications Trends
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• v.37 no.1
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• pp.42-52
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• 2022

With the advent of the big data era, the memory capacity required for computing systems is rapidly increasing, especially in High Performance Computing systems. However, the number of DRAMs that can be used in a computing node is limited by the structural limitations of the hardware (for example, CPU specifications). Memory expansion technology has attracted attention as a means of overcoming this limitation. This technology expands the memory capacity by leveraging the external memory connected to the host system through hardware interface such as PCIe and CCIX. In this paper, we present an overview and describe the development trends of the memory expansion technology. We also provide detailed descriptions and use cases of the CCIX that provides higher bandwidth and lower latency than cases of the PCIe.

• KIISE Transactions on Computing Practices
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• v.24 no.1
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• pp.10-16
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• 2018

The task of consolidating server workloads is critical for the efficiency of a datacenter in terms of reducing costs. However, as a greater number of workloads are consolidated in a single server, the performance of workloads might be degraded due to their contention to the limited shared resources. To reduce the performance degradation, scheduling for mitigating the contention of shared resources is necessary. In this paper, we present the Dynamic Voltage Frequency Scaling (DVFS) based memory-contention aware scheduling method for multi-threaded workloads. The proposed method uses two approaches: running memory-intensive threads on the limited cores to avoid concurrent memory accesses, and reducing the frequencies of the cores that run memory-intensive threads. With the proposed algorithm, we increased performance by 43% and reduced power consumption by 38% compared to the Completely Fair Scheduler(CFS), the default scheduler of Linux.

• Computational Structural Engineering
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• v.4 no.2
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• pp.103-110
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• 1991

To solve the large problems with limited core memory of computer, a disk management scheme called virtual memory database has been developed. Utilizing this technique along with memory moving scheme, an efficient in-and out-of-core column solver for the sparse symmetric matrix commonly arising in the finite element analysis is developed. Compared with other methods the algorithm is simple, therefore the coding and computational efficiencies are greatly enhanced. Analysis example shows that the proposed method efficiently solve the large structural problem on the small-memory micro-computer.

• IMMUNE NETWORK
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• v.15 no.4
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• pp.186-190
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• 2015

Cytomegalovirus (CMV) infection in healthy individuals is usually asymptomatic and results in latent infection. CMV reactivation occasionally occurs in healthy individuals according to their immune status over time. T cell responses to CMV are restricted to a limited number of immunodominant epitopes, as compared to responses to other chronic or persistent viruses. This response results in progressive, prolonged expansion of CMV-specific $CD8^+$ T cells, termed 'memory inflation'. The expanded CMV-specific $CD8^+$ T cell population is extraordinarily large and is more prominent in the elderly. CMV-specific $CD8^+$ T cells possess rather similar phenotypic and functional features to those of replicative senescent T cells. In this review, we discuss the general features of CMV-specific inflationary memory T cells and the factors involved in memory inflation.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.3
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• pp.59-67
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• 2009

This paper proposes a improved bitmap routing protocol, which finds the best energy efficient routing path by minimizing the network overheads and prolongs the overall network lifetime. Jung proposed a bitmap scheme for sensor networks. His scheme uses a bitmap table to represent the connection information between nodes. However, it has a problem that the table size is depends on the number of nodes in the sensor networks. The problem is very serious in the sensor node with a limited memory. Thereby, this paper proposes a improved bitmap routing protocol to solve the problem in Jung's scheme. Proposed protocol over the memory restricted sensor network could optimize the size of bitmap table by applying the deployed network property. Proposed protocol could be used in the diversity of sensor networks due to it has minimum memory overheads.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.330-338
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• 2016

Phase change memory (PCM) has been studied as an emerging memory technology for last-level cache (LLC) due to its extremely low leakage. However, it consumes high levels of energy in updating cells and its write endurance is limited. To relieve the write pressure of LLC, we propose a delta value indicator (DVI) by employing a small cache which stores the difference between the value currently stored and the value newly loaded. Since the write energy consumption of the small cache is less than the LLC, the energy consumption is reduced by access to the small cache instead of the LLC. In addition, the lifetime of the LLC is further extended because the number of write accesses to the LLC is decreased. To this end, a delta value indicator and controlling circuits are inserted into the LLC. The simulation results show a 26.8% saving of dynamic energy consumption and a 31.7% lifetime extension compared to a state-of-the-art scheme for PCM.

• Proceedings of the Korea Society for Simulation Conference
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• 2003.11a
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• pp.67-74
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• 2003

Stream servers are for supplying multimedia stream data to users through the internet such as movies and musics without discontinuation. A typical stream server is designed roughly by considering the characteristics of stream services and by employing processors, memory, PCI bus, Ethernet, TOE and disks. This study focuses on deciding the priority for using resources such as PCI bus, buffer memory and TOE buffer, which have limited capacities in a typical stream server. The simulation study shows that the top priority for using PCI bus for normal streaming services should be given to the operation that sends data from buffer memory to TOE buffer Giving priority for using PCI bus to other operation such as sending data from disks to memory results in deadlock Phenomenon.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.1
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• pp.59-65
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• 2022

Virtual memory is used as the method to ensure the safety of the system through memory protection in the real-time system. TLB miss caused by using virtual memory makes the real-time system WCET more pessimistically. TLB lockdown can be applied as a method to improve this problem. However, processors with limited TLB lockdown entries, a selection criterion is needed to efficiently utilize the TLB lockdown entry. In this paper, the most frequently accessed virtual pages in the process are applied to the TLB lockdown by analyzing memory profiling. The results showed that micro data TLB miss stall cycle and main data TLB miss stall cycle of the processor decreased by at least 4.7% and up to 29.7%.