• Macromolecular Research
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• 제16권7호
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• pp.644-650
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• 2008

This study examined the effect of nanoclays on the shape memory behavior of polyurethane (PU) in fibrous form. A cation was introduced into the PU molecules to disperse the organo-nanoclay (MMT) into poly($\varepsilon$-caprolactone) (PCL)-based PU (PCL-PU). The MMT/PCL-PU nanocomposites were then spun into fibers through melt-processing. The shape memory performance of the spun fibers was examined using a variety of thermo-mechanical tests including a new method to determine the transition temperature of shape memory polymers. The MMTs showed an improved the fixity strain rate of the MMT /PCL- PU fibers but a slight decrease in their recovery strain rate. This was explained by the limited movement of PU molecules due to the presence of nanoclays. The shape memory performance of the MMT/PCL-PU fibers was not enhanced significantly by the nanoclays. However, their recovery power was improved significantly up to a strain of approximately 50%.

• 한국산업융합학회 논문집
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• 제24권1호
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• pp.69-77
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• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.

• 전자통신동향분석
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• 제37권1호
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• pp.42-52
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• 2022

With the advent of the big data era, the memory capacity required for computing systems is rapidly increasing, especially in High Performance Computing systems. However, the number of DRAMs that can be used in a computing node is limited by the structural limitations of the hardware (for example, CPU specifications). Memory expansion technology has attracted attention as a means of overcoming this limitation. This technology expands the memory capacity by leveraging the external memory connected to the host system through hardware interface such as PCIe and CCIX. In this paper, we present an overview and describe the development trends of the memory expansion technology. We also provide detailed descriptions and use cases of the CCIX that provides higher bandwidth and lower latency than cases of the PCIe.

• 정보과학회 컴퓨팅의 실제 논문지
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• 제24권1호
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• pp.10-16
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• 2018

비용절감을 위해 제한된 서버 워크로드를 통합하는 것은 데이터센터의 효율성에 중요하다. 하지만 더 많은 워크로드가 하나의 서버에 통합되면서, 워크로드들의 성능이 제한된 공유 자원에 대한 경합으로 인해 감소될 수 있다. 이러한 성능감소를 줄이기 위해서 공유자원에 대한 경합을 줄이는 스케줄이 필요하다. 본 논문에서는 이러한 공유자원, 특히 메모리 서브시스템에 대해서 경합을 줄일 수 있는 DVFS(Dynamic Voltage Frequency Scaling) 기반의 메모리 인지 쓰레드 스케줄링 방법을 제안한다. 제안한 알고리즘은 메모리 자원에 대한 경합을 줄이기 위해서, 메모리 자원에 대한 접근을 제한하는 방식으로 두 가지 방법을 사용한다. 메모리 인텐시브 쓰레드를 제한된 코어에서 수행하고, 메모리 인텐시브 쓰레드가 수행되는 코어의 주파수를 낮추어 경합을 완화한다. 제안한 알고리즘을 적용하여 쓰레드 스케줄링 시, 리눅스의 CFS(Completely Fair Scheduler) 대비 최대 43%의 성능향상을 이루고 파워소모를 38% 줄일 수 있었다.

• 전산구조공학
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• 제4권2호
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• pp.103-110
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• 1991

컴퓨터의 제한된 코어메모리로 대형문제를 해결하기 위하여 디스크를 마치 메모리처럼 사용할 수 있는 가상 메모리 데이타베이스 기법을 개발하였다. 이 기법과 아울러 최대 가용코어메모리를 작동시키는 방식을 사용하여 유한요소 해석시 흔히 발생하는 스카이라인 형태로 저장된 대칭통산행예(Sparse Symmetric Matrix)에 대한 매우 효과적인 코어 내 및 코어 외 직립방정식의 해법을 개발하였다. 제안된 방법은 다른 코어 외 해법에 비해 알고리즘 및 코딩이 매우 간단하여 계산효율을 상당히 향상시켰다. 해석예에서는 제안된 방법을 사용하여 대규모 구조해석 문제를 메모리 용량이 작은 소형컴퓨터에서 대단히 효율적으로 해결하였음을 보여주었다.

• IMMUNE NETWORK
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• 제15권4호
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• pp.186-190
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• 2015

Cytomegalovirus (CMV) infection in healthy individuals is usually asymptomatic and results in latent infection. CMV reactivation occasionally occurs in healthy individuals according to their immune status over time. T cell responses to CMV are restricted to a limited number of immunodominant epitopes, as compared to responses to other chronic or persistent viruses. This response results in progressive, prolonged expansion of CMV-specific $CD8^+$ T cells, termed 'memory inflation'. The expanded CMV-specific $CD8^+$ T cell population is extraordinarily large and is more prominent in the elderly. CMV-specific $CD8^+$ T cells possess rather similar phenotypic and functional features to those of replicative senescent T cells. In this review, we discuss the general features of CMV-specific inflationary memory T cells and the factors involved in memory inflation.

• 디지털산업정보학회논문지
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• 제5권3호
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• pp.59-67
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• 2009

This paper proposes a improved bitmap routing protocol, which finds the best energy efficient routing path by minimizing the network overheads and prolongs the overall network lifetime. Jung proposed a bitmap scheme for sensor networks. His scheme uses a bitmap table to represent the connection information between nodes. However, it has a problem that the table size is depends on the number of nodes in the sensor networks. The problem is very serious in the sensor node with a limited memory. Thereby, this paper proposes a improved bitmap routing protocol to solve the problem in Jung's scheme. Proposed protocol over the memory restricted sensor network could optimize the size of bitmap table by applying the deployed network property. Proposed protocol could be used in the diversity of sensor networks due to it has minimum memory overheads.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.330-338
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• 2016

Phase change memory (PCM) has been studied as an emerging memory technology for last-level cache (LLC) due to its extremely low leakage. However, it consumes high levels of energy in updating cells and its write endurance is limited. To relieve the write pressure of LLC, we propose a delta value indicator (DVI) by employing a small cache which stores the difference between the value currently stored and the value newly loaded. Since the write energy consumption of the small cache is less than the LLC, the energy consumption is reduced by access to the small cache instead of the LLC. In addition, the lifetime of the LLC is further extended because the number of write accesses to the LLC is decreased. To this end, a delta value indicator and controlling circuits are inserted into the LLC. The simulation results show a 26.8% saving of dynamic energy consumption and a 31.7% lifetime extension compared to a state-of-the-art scheme for PCM.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 2003년도 추계학술대회 및 정기총회
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• pp.67-74
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• 2003

Stream servers are for supplying multimedia stream data to users through the internet such as movies and musics without discontinuation. A typical stream server is designed roughly by considering the characteristics of stream services and by employing processors, memory, PCI bus, Ethernet, TOE and disks. This study focuses on deciding the priority for using resources such as PCI bus, buffer memory and TOE buffer, which have limited capacities in a typical stream server. The simulation study shows that the top priority for using PCI bus for normal streaming services should be given to the operation that sends data from buffer memory to TOE buffer Giving priority for using PCI bus to other operation such as sending data from disks to memory results in deadlock Phenomenon.

• 대한임베디드공학회논문지
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• 제17권1호
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• pp.59-65
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• 2022

Virtual memory is used as the method to ensure the safety of the system through memory protection in the real-time system. TLB miss caused by using virtual memory makes the real-time system WCET more pessimistically. TLB lockdown can be applied as a method to improve this problem. However, processors with limited TLB lockdown entries, a selection criterion is needed to efficiently utilize the TLB lockdown entry. In this paper, the most frequently accessed virtual pages in the process are applied to the TLB lockdown by analyzing memory profiling. The results showed that micro data TLB miss stall cycle and main data TLB miss stall cycle of the processor decreased by at least 4.7% and up to 29.7%.